 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2009, zarlink semiconductor inc. all rights reserved. features general ? circuit emulation services over packet (cesop) transport for mpls, ip and ethernet networks ? on chip timing & synchronization recovery across a packet network ? grooming capability for nx64 kbps trunking circuit emulation services ? supports itu-t recommendation y.1413 and y.1453 ? supports ietf rfc4553 and rfc5086 ? supports mef8 and mfa 8.0.0 ? structured, synchronous cesop with clock recovery ? unstructured, asynchronous cesop, with integral per stream clock recovery tdm interfaces ? up to 32 t1/e1, 8 j2, or 2 t3/e3 ports ? h.110, h-mvip, st-bus backplanes ? up to 1024 bi-directional 64 kbps channels ? direct connection to lius, framers, backplanes ? dual reference stratum 4 and 4e dpll for synchronous operation network interfaces ? up to 3 x 100 mbps mii fast ethernet or dual redundant 1000 mbps gmii/tbi ethernet interfaces system interfaces ? flexible 32 bit host cpu interface (motorola powerquicc ? compatible) ? on-chip packet memory for self-contained operation, with buffer depths of over 16 ms ? up to 8 mbytes of off-chip packet memory, supporting buffer depths of over 128 ms october 2009 ordering information zl50110gag 552 pbga trays, bake & drypack zl50111gag 552 pbga trays, bake & drypack zl50112gag 552 pbga trays, bake & drypack zl50114gag 552 pbga trays, bake & drypack zl50110gag2 552 pbga** trays, bake & drypack ZL50111GAG2 552 pbga** trays, bake & drypack zl50112gag2 552 pbga** trays, bake & drypack zl50114gag2 552 pbga** trays, bake & drypack **pb fee tin silver/copper -40c to +85c zl50110/11/12/14 128, 256, 512 and 1024 channel cesop processors data sheet figure 1 - zl50111 high level overview on chip packet memory (jitter buffer compensation for 16-128 ms of packet delay variation) dual reference dpll host processor interface external mem ory interface (optional) h.110, h-mvip, st-bus backplanes triple 100 mbps mii fast ethernet or dual redudnat 1000 mbps gmii/ tbi gigabit ethernet backplane clocks 32-bit motorola compatible pqii? multi-protocol packet processing engine pw , rtp, udp, ipv4, ipv6, m pls, ecid, vlan, user defined, others triple packet interface mac (m ii, g m ii, tbi) tdm interface (liu, framer, backplane) per port dco for clock recovery zbt-sram (0 - 8 mbytes) 32 t1/e1, 8 j2, 2 t3/e3 ports
zl50110/11/12/14 data sheet 2 zarlink semiconductor inc. packet processing functions ? flexible, multi-protocol packet encapsulation including support for ipv4, ipv6, rtp, mpls, l2tpv3, itu-t y.1413, rfc4553, rfc5086 and user programmable ? packet re-sequencing to allow lost packet detection ? four classes of service with programmable prio rity mechanisms (wfq and sp) using egress queues ? flexible classification of incoming packets at layers 2, 3, 4 and 5 ? supports up to 128 separate cesop connections across the packet switched network applications ? circuit emulation services over packet networks ? leased line support over packet networks ? multi-tenant unit access concentration ? tdm over cable ? fibre to the premises g/e-pon ? layer 2 vpn services ? customer-premise and provider edge routers and switches ? packet switched backplane applications zl50110/11/12/14 data sheet 3 zarlink semiconductor inc. description the zl50110/11/12/14 family of cesop processors are highly functional tdm to packet bridging devices. the zl50110/11/12/14 provides both structur ed and unstructured circuit emulation services over packet (cesop) for up to 32 t1, 32 e1 and 8 j2 streams across a packet network based on mpls, ip or ethernet. the zl50111 also supports unstructured t3 and e3 streams. the circuit emulation features in the zl50110/11/12/14 family supports the itu recommendations y.1413 and y.1453, as well as the cesop standards from the metro ethernet forum (mef) and mpls and frame relay alliance. the zl50110/11/14 also supports ietf rfc4553 and rfc5086. the zl50110/11/12/14 provides up to triple 100 mbps mii ports or dual redundan t 1000 mbps gmii/tbi ports. the zl50110/11/12/14 incorporates a range of powerful cl ock recovery mechanisms for each tdm stream, allowing the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance and quality. timing is carried using rtp or similar prot ocols, and both adaptive and differential clock recovery schemes are included, allowing the customer to choose the correct scheme for the application. an externally supplied clock may also be used to drive the tdm interface of the zl50110/11/12/14. the zl50110/11/12/14 incur very low latency for the data flow, thereby increasing qos when carrying voice services across the packet switched network. voice, when carried using cesop, which typically has latencies of less than 10 ms, does not require expensive processing such as compression and echo cancellation. the zl50110/11/12/14 is capable of assembling user-defi ned packets of tdm traffic from the tdm interface and transmitting them out the packet interf aces using a variety of protocols. t he zl50110/11/12/14 supports a range of different packet switched networks, including ethernet vlans, ip and mpls. the zl50110/11/12/14 can support up to 4 pr otocol stacks at the same time, prov ided that each protocol stack can be uniquely identified by a mask & match approach. packets received from the packet interfaces are pars ed to determine the egress des tination, and are appropriately queued to the tdm interface, they can also be forwarded to the host interface, or back toward the packet interface. packets queued to the tdm interface can be re-ordered based on sequence num ber, and lost packets filled in to maintain timing integrity. the zl50110/11/12/14 family includes su fficient on-chip memory that external memory is not required in most applications. this reduces system co sts and simplifies the design. for applications that do require more memory (e.g., high stream count or hi gh latency), the device supports up to 8 mbytes of ssram. a comprehensive evaluation system is available upon request from your local zarlink re presentative or distributor. this system includes the cesop processor, various tdm interfaces and a fully featured evaluation software gui that runs on a windows pc. zl50110/11/12/14 data sheet 4 zarlink semiconductor inc. device line up there are four products within the zl50110/11/12/14 fa mily, with capacity as shown in the following table: note 1: t1/e1/j2 is for unstructured mode, and the h-mvip/h.110/st-bus is for structured mode. device tdm interfaces ethernet packet i/f notes zl50114 4 t1, 4 e1, or 1 j2 streams or 4 mvip/st-bus streams at 2.048 mbps or 1 h.110/h-mvip/st-bus streams at 8.192 mbps dual 100 mbps mii or dual redundant 1000 mbps gmii/tbi note 1 zl50110 8 t1, 8 e1 or 2 j2 streams or 8 mvip/st-bus streams at 2.048 mbps or 2 h.110/h-mvip/st-bus streams at 8.192 mbps dual 100 mbps mii or dual redundant 1000 mbps gmii/tbi note 1 zl50112 16 t1, 16 e1, 4 j2 streams or 16 mvip/st-bus streams at 2.048 mbps or 4 h.110/h-mvip/st-bus streams at 8.192 mbps triple 100 mbps mii or dual redundant 1000 mbps gmii/tbi or single 100 mbps mii and single 1000 mbps gmii/tbi note 1 zl50111 32 t1, 32 e1, 8 j2, 2 t3, 2 e3 streams or 32 mvip/st-bus streams at 2.048 mbps or 8 h.110/h-mvip/st-bus streams at 8.192 mbps triple 100 mbps mii or dual redundant 1000 mbps gmii/tbi or single 100 mbps mii and single 1000 mbps gmii/tbi note 1 table 1 - capacity of devices in the zl50110/11/14 family zl50110/11/12/14 data sheet table of contents 5 zarlink semiconductor inc. 1.0 changes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.0 physical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0 external interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 tdm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.1 zl50111 variant tdm stream connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.1.2 zl50112 variant tdm stream connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.1.3 zl50110 variant tdm stream connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.1.4 zl50114 variant tdm stream connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.1.5 tdm signals common to zl50110, zl50111, zl50112 and zl50114 . . . . . . . . . . . . . . . . . . . . . . 31 3.2 pac interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 packet interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5 cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.6 system function interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.7 test facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.7.1 administration, control and test interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.7.2 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.8 miscellaneous inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.9 power and ground connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.10 zl50111, zl50112, zl50110 and za50114 internal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.11 zl50112 internal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.12 zl50112 auxiliary clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.0 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.1 leased line provision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2 metropolitan area network aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3 digital loop carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.4 remote concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.5 cell site backhaul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.6 equipment architecture example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 data and control flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3 tdm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.1 tdm interface block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.2 structured tdm port data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3.3 tdm clock structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.3.1 synchronous tdm clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.3.2 asynchronous tdm clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.4 payload assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.4.1 structured payload operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.4.1.1 structured payload order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.4.2 unstructured payload operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.5 protocol engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.6 packet transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.7 packet reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.8 tdm formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.0 clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.1 differential clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 adaptive clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3 system_clk considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.0 system features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 zl50110/11/12/14 data sheet table of contents 6 zarlink semiconductor inc. 7.1 latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.2 loopback modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.3 host packet generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.4 loss of service (los) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5 external memory requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.6 gigabit ethernet - recommended configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.6.1 central ethernet switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.6.2 redundant ethernet switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.7 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.8 jtag interface and board level test features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.9 external component requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.9.1 host processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.9.2 other components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.10 miscellaneous features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.11 test modes operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.11.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.11.1.1 system normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.11.1.2 system tri-state mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.11.2 test mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.11.3 system normal mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.11.4 system tri-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.0 dpll specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.1.1 locking mode (normal operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.1.2 holdover mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.1.3 freerun mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.1.4 powerdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.2 reference monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.3 locking mode reference switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.4 locking range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.5 locking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.6 lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.7 jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.7.1 acceptance of input wander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.7.2 intrinsic jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.7.3 jitter tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.7.4 jitter transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.8 maximum time interval error (mtie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.0 memory map and register definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.0 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.0 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.1 tdm interface timing - st-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.1.1 st-bus slave clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.1.2 st-bus master clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.2 tdm interface timing - h.110 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.3 tdm interface timing - h-mvip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.4 tdm liu interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.5 pac interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.6 packet interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.6.1 mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.6.2 mii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.6.3 gmii transmit timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 zl50110/11/12/14 data sheet table of contents 7 zarlink semiconductor inc. 11.6.4 gmii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.6.5 tbi interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.6.6 management interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.7 external memory interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.8 cpu interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.9 system function port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.10 jtag interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.0 power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.0 design and layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.1 high speed clock & data interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.1.1 external memory interface - spec ial considerations during layout. . . . . . . . . . . . . . . . . . . . . . . . 105 13.1.2 gmac interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.1.3 tdm interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 13.1.4 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.2 cpu ta output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.3 mx_linkup_led outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 14.0 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.1 external standards/specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.2 zarlink standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 15.0 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 zl50110/11/12/14 data sheet list of figures 8 zarlink semiconductor inc. figure 1 - zl50111 high level overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - zl50111 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3 - zl50112 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4 - zl50110 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5 - zl50114 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6 - leased line services over a circuit emulation link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 7 - metropolitan area network aggregation using cesop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 8 - digital loop carrier using cesop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 9 - remote concentrator using cesop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 10 - cell site backhaul using cesop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 11 - equipment example using cesop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 12 - zl50110/11/12/14 family operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 13 - zl50110/11/12/14 data and control flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 14 - synchronous tdm clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 15 - zl50110/11/12/14 packet format - structured mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 16 - channel order for packet formation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 17 - zl50110/11/12/14 packet format - unstructured mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 18 - differential clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 19 - adaptive clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 20 - external memory requirement for zl50111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 21 - external memory requirement for zl50110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 22 - gigabit ethernet co nnection - central ethernet switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 23 - gigabit ethernet co nnection - redundant ethernet switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 24 - powering up the zl50110/11/12/14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 25 - jitter transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 26 - jitter transfer function - detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 27 - tdm st-bus slave mode timing at 8.192 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 28 - tdm st-bus slave mode timing at 2.048 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 29 - tdm bus master mode timing at 8.192 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 30 - tdm bus master mode timing at 2.048 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 31 - h.110 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 32 - tdm - h-mvip timing diagram for 16 mhz clock (8.192 mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 33 - tdm-liu structured transmission/reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 34 - mii transmit timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 35 - mii receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 36 - gmii transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 37 - gmii receive timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 38 - tbi transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 39 - tbi receive timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 40 - management interface timing for ethernet port - r ead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 41 - management interface timing for ethernet port - wr ite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 42 - external ram read and write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 43 - cpu read - mpc8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 44 - cpu write - mpc8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 45 - cpu dma read - mpc8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 46 - cpu dma write - mpc8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 47 - jtag signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 48 - jtag clock and reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 zl50110/11/12/14 data sheet list of figures 9 zarlink semiconductor inc. figure 49 - zl50110/11/12/14 power consumption plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 50 - cpu_ta board circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 51 - mx_linkup_led stuffing option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 zl50110/11/12/14 data sheet list of tables 10 zarlink semiconductor inc. table 1 - capacity of devices in the zl50110/11/14 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2 - tdm interface zl50111 stream pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 3 - tdm interface zl50112 stream pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 4 - tdm interface zl50110 stream pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5 - tdm interface zl50114 stream pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6 - tdm interface common pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7 - pac interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8 - packet interface signal mapping - mii to gmii/tbi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9 - mii management interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10 - mii port 0 interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11 - mii port 1 interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 12 - mii port 2 interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13 - mii port 3 interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14 - external memory interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 15 - cpu interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 16 - system function interface package ball definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 17 - administration/control interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 18 - jtag interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 19 - miscellaneous inputs package ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 20 - power and ground package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 21 - no connection ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 22 - no connection ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 23 - auxiliary clock ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 24 - standard device flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 25 - tdm services offered by the zl50110/11/12/14 family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 26 - some of the tdm port formats accepted by the zl50110/11/12/14 family . . . . . . . . . . . . . . . . . . . . 60 table 27 - dma maximum bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 28 - test mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 29 - dpll input reference frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 30 - tdm st-bus master timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 31 - tdm h.110 timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 32 - tdm h-mvip timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 33 - tdm - liu structured transmission/reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 34 - pac timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 35 - mii transmit timing - 100 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 36 - mii receive timing - 100 mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 37 - gmii transmit timing - 1000 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 38 - gmii receive timing - 1000 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 39 - tbi timing - 1000 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 40 - mac management timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 41 - external memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 42 - cpu timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 43 - system clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 44 - jtag interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 45 - mx_linkup_led pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 46 - mx_linkup_led stuffing option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 zl50110/11/12/14 data sheet 11 zarlink semiconductor inc. 1.0 changes summary the following table captures the changes from the march 2009 issue. the following table captures the changes from the january 2009 issue. the following table captures the changes from the april 2008 issue. the following table captures the changes from the october 2006 issue. page item change 1 mef logo added mef logo to show mef 18 certification. page item change 61 & 64 section 5.4 and section 5.8 replaced zlan- 202 with zl5011x design manual section ?13.1 understanding forcedelete?. 67 section 6.3 replaced zlan-143 with zl5011x design manual section ?3.6 system clock block.? 69 section 7.4 replaced zlan-159 with zl5011x design manual section ?3.1.1 connection to liu?. 94 section 11.6.5 replaced zlan-239 with zl5011x design manual section ?7.1.3.1 tbi interface timing?. 109 section 14.1 removed references to ietf pwe3 draft-ietf-l2tpext-l2tp-base and ietf pwe3 draft-ietf-pwe3-cesop. page item change 68 section 7.3 add note 3 page item change several include zl50112 device add description for zl50112 1, 2 and 3 standard updated ietf rfc number and standards in general 1, 58, 74, 75 and 77 stratum 3 dpll updated the description for stratum 3 dpll 1, 4, 24, 52 and 59 sts-1 stream remove sts-1 stream 14 section 2.0 combine the packaged descriptions for all devices 33 section 3.3 include more detailed description for the packet interface 49 section 3.7.2 zl50112 and zl50111 share the same jtag id 56 section 4.6 change the title of the section 57 section 5.0 add a note about jumbo packets 59 section 5.3 include a paragraph to clarify the support for structure and unstructure modes at the same time 61 section 5.4 include more detailed description for the payload assembly 63 section 5.4.2 add a note at the end of the section 64 section 5.8 include more detailed description for the tdm formatter zl50110/11/12/14 data sheet 12 zarlink semiconductor inc. the following table captures the changes from the february 2006 issue. the following table captures the changes from the april 2005 issue. the following table captures the changes from the january 2005 issue. 65 section 6.0 include more detailed description for clock recovery 65 section 6.1 include more detailed description for differential clock recovery 66 section 6.2 updated the description of adaptive clock recovery 73 section 7.9 added sub sections 87 table 32 tdm_hds input setup and tdm_hds input hold, max. time corrected. 94 section 11.6.5 updated txd[9:0] output delay 95 section 11.6.6 updatedsection 11.6.6 management interface timing (m_mdio hold time and figure 40) 97 figure 43 and figure 44 cpu_ts _ale and cpu_ta. added mode details in figure 43 and figure 44 added the cpu_ta assertion time. page item change 96 table 41, table 41 - external memory timing added minimum values page item change clarified zl50111 supports 3 mii ports, zl50110/4 support 2 mii ports. 48, 49 section 3.6 and section 3.7.2 added external pull-up/pull-down resistor recommendations for system_rst, system_debug, jtag_trst, jtag_tck. 67 section 6.3 added section 6.3 system_clk considerations. page item change clarified data sheet to indicate zl50110/11/12/14 supports clock recovery in both synchronous and asynchronous modes of operation. 99 figure 45 inverted polarity of cpu_dreq0 and cpu_dreq1 to conform with default mpc8260. polarity of cpu_dreq and cpu_sdack remains programmable through api. 99 figure 46 inverted polarity of cpu_dreq0 and cpu_dreq1 to conform with default mpc8260. polarity of cpu_dreq and cpu_sdack remains programmable through api. page item change zl50110/11/12/14 data sheet 13 zarlink semiconductor inc. the following table captures the changes from the october 2004 issue. the following table captures the changes from the september 2004 issue. page item change 49 section 3.7.1 added 5 kohm pulldown recommendation to gpio signals. page item change 12, 16, 19 fig. 2 and ball signal assignment table corrected mx_linkup_led pin assignment. 73 dc electrical characteristics table and output levels table changed electrical characteristics to differentiate between 3.3 v and 5 v tolerant signals. 98 section 13.3 new section added; mx_linkup_led outputs. zl50110/11/12/14 data sheet 14 zarlink semiconductor inc. 2.0 physical specification the zl50110/11/12/14 is packaged in a pbga device. features: ? body size: 35 mm x 35 mm (typ) ? ball count: 552 ? ball pitch: 1.27 mm (typ) ? ball matrix: 26 x 26 ? ball diameter: 0.75 mm (typ) ? total package thickness: 2.33 mm (typ) zl50110/11/12/14 data sheet 15 zarlink semiconductor inc. zl50111 package view from top side. note that ball a1 is non-chamfered corner. figure 2 - zl50111 package view and ball positions a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af gnd tdm_sto[ 1] tdm_clk o[3] tdm_sto[ 4] tdm_sto[ 5] tdm_sti[ 6] tdm_sto[ 7] tdm_sti[ 7] tdm_clk o[10] tdm_clki [10] tdm_clki [11] tdm_clk o[13] gnd tdm_sto[ 13] tdm_sto[ 14] tdm_clk o[15] tdm_sto[ 16] tdm_clk o[18] tdm_sti[ 18] tdm_clki [20] tdm_sti[ 20] tdm_sto[ 21] tdm_sti[ 21] tdm_clk o[24] tdm_clk o[25] gnd 1 2 3 4 5 6 7 8 91011121314151617181920212223242526 tdm_frm o_ref tdm_sto[ 0] tdm_sti[ 2] tdm_clki [3] tdm_sti[ 4] tdm_clk o[6] tdm_sto[ 6] tdm_clk o[8] tdm_clki [9] tdm_sto[ 10] tdm_sti[ 10] tdm_clki [12] tdm_sto[ 12] tdm_sti[ 13] tdm_clki [15] tdm_sti[ 15] tdm_sti[ 17] tdm_clki [18] tdm_clk o[20] tdm_sto[ 19] tdm_sto[ 22] tdm_clk o[23] tdm_sto[ 24] tdm_clk o[26] tdm_sti[ 24] tdm_clk o[27] tdm_clki p tdm_frm i_ref tdm_clki _ref tdm_clk o[1] tdm_sti[ 3] tdm_clk o[2] tdm_clki [6] tdm_clki [7] tdm_clk o[9] tdm_sto[ 9] tdm_sti[ 9] tdm_sti[ 11] tdm_clki [13] tdm_clk o[14] tdm_clk o[16] tdm_sti[ 16] tdm_clk o[17] tdm_sti[ 19] tdm_clk o[21] tdm_clki [21] tdm_clki [24] tdm_sti[ 22] tdm_sto[ 26] tdm_clki [27] tdm_sti[ 27] tdm_sti[ 28] ram_dat a[3] ram_dat a[1] tdm_clki s ram_dat a[0] tdm_sti[ 0] tdm_clki [1] tdm_sto[ 3] tdm_sti[ 5] tdm_clki [5] tdm_clk o[7] tdm_sti[ 8] tdm_clk o[11] tdm_sti[ 12] tdm_sti[ 14] tdm_clki [16] tdm_clk o[19] tdm_sto[ 18] tdm_sto[ 20] tdm_clk o[22] tdm_sto[ 27] tdm_sto[ 25] tdm_clki [26] tdm_clk o[28] tdm_clki [29] tdm_sti[ 29] tdm_sti[ 31] ram_dat a[10] ram_dat a[9] ram_dat a[5] ram_dat a[4] ram_dat a[2] tdm_clk o_ref tdm_clki [0] tdm_clk o[4] tdm_sti[ 1] tdm_clki [4] tdm_sto[ 8] tdm_clki [8] tdm_clk o[12] tdm_sto[ 15] tdm_clki [17] tdm_clki [19] tdm_sto[ 23] tdm_sti[ 23] tdm_clki [25] tdm_sti[ 26] tdm_clki [28] gnd tdm_clk o[30] tdm_clki [30] tdm_sti[ 30] tdm_sto[ 29] ram_dat a[15] ram_dat a[13] ram_dat a[12] ram_dat a[6] ram_dat a[7] gnd vdd_cor e tdm_sto[ 2] tdm_clk o[0] tdm_clki [2] tdm_clk o[5] vdd_cor e tdm_sto[ 11] tdm_clki [14] tdm_sto[ 17] tdm_clki [22] tdm_sti[ 25] tdm_clki [23] vdd_cor e gnd tdm_clki [31] tdm_clk o[29] tdm_sto[ 28] tdm_clk o[31] m1_linku p_led ram_dat a[21] ram_dat a[18] ram_dat a[16] ram_dat a[14] ram_dat a[11] ram_dat a[8] tdm_sto[ 31] tdm_sto[ 30] m2_linku p_led m3_linku p_led m1_giga bit_led m_mdio ram_dat a[25] ram_dat a[24] ram_dat a[23] ram_dat a[19] ram_dat a[17] vdd_cor e vdd_cor e m0_giga bit_led m_mdc m3_crs m3_txcl k m3_rxer ram_dat a[29] ram_dat a[28] ram_dat a[27] ram_dat a[26] ram_dat a[22] ram_dat a[20] vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io m3_rxdv m3_rxd[3 ] m3_rxd[2 ] m3_rxd[1 ] m3_rxd[0 ] m3_col ram_par ity[1] ram_par ity[0] ram_dat a[31] ram_dat a[30] gnd vdd_cor e vdd_io vdd_cor e gnd m3_txd[3 ] m3_txen m3_txer m3_rxcl k ram_par ity[7] ram_par ity[6] ram_par ity[5] ram_par ity[4] ram_par ity[3] ram_par ity[2] vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_rxer m1_txcl k m1_crs m3_txd[0 ] m3_txd[1 ] m3_txd[2 ] ram_add r[5] ram_add r[4] ram_add r[2] ram_add r[3] ram_add r[0] ram_add r[1] vdd_io gnd gnd gnd gnd gnd gnd vdd_io vdd_cor e m1_refc lk m1_rxcl k m1_rxd[5 ] m1_rxd[7 ] m1_rxdv gnd ram_add r[6] ram_add r[7] ram_add r[8] gnd vdd_cor e vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_gtx_ clk gnd m1_txer m1_rxd[2 ] m1_rxd[3 ] gnd ram_add r[9] ram_add r[10] ram_add r[11] ram_add r[13] ram_add r[16] gnd vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_txd[2 ] m1_txd[6 ] m1_txen gnd m1_rxd[4 ] m1_rxd[6 ] ram_add r[12] ram_add r[14] ram_add r[15] ram_add r[19] ic_gnd ic vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_txd[0 ] m1_txd[3 ] m1_txd[5 ] m1_txd[7 ] m1_col m1_rxd[1 ] ram_add r[17] ram_add r[18] ram_bw _b ic_gnd gnd a1vdd vdd_io gnd gnd gnd gnd gnd gnd vdd_io vdd_cor e m1_txd[1 ] m1_txd[4 ] gnd m1_rbc1 m1_rxd[0 ] pll_pri ram_bw _a ram_bw _c ram_rw system_ debug system_ clk vdd_io vdd_io m0_gtx_ clk m0_rxd[2 ] m0_rxd[5 ] m0_txcl k m0_crs m1_rbc0 pll_sec ram_bw _d ram_bw _f system_ rst gpio[2] vdd_cor e vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io m0_txd[7 ] m0_txer m0_txen m0_rxd[4 ] m0_rxdv m0_rxer ram_bw _e ram_bw _g gpio[0] gpio[3] gpio[9] ram_dat a[33] m0_txd[2 ] m0_txd[5 ] m0_txd[6 ] m0_rxd[6 ] m0_rxd[7 ] m0_rxd[3 ] ram_bw _h gpio[4] gpio[6] gpio[10] ram_dat a[32] vdd_cor e vdd_cor e m0_txd[1 ] m0_txd[4 ] m0_rbc0 m0_col m0_rxd[1 ] gpio[1] gpio[7] gpio[8] gpio[15] ram_dat a[39] gnd ram_dat a[45] ram_dat a[52] vdd_cor e jtag_tm s cpu_add r[2] cpu_add r[12] vdd_cor e vdd_cor e cpu_dat a[8] cpu_dat a[15] cpu_dat a[23] vdd_cor e m2_rxcl k m2_rxdv gnd m0_txd[0 ] m0_txd[3 ] m0_refc lk m0_rbc1 m0_rxd[0 ] gpio[5] gpio[11] gpio[14] ram_dat a[38] ram_dat a[43] ram_dat a[44] ram_dat a[51] ram_dat a[60] test_mo de[1] gnd cpu_add r[6] cpu_add r[14] cpu_add r[23] cpu_ta cpu_dat a[1] cpu_dat a[7] cpu_dat a[12] cpu_dat a[22] cpu_dat a[30] m2_txer m2_rxd[1 ] m0_rxcl k m0_linku p_led m2_activ e_led m1_activ e_led m3_activ e_led gpio[12] gpio[13] ram_dat a[37] ram_dat a[42] ram_dat a[46] ram_dat a[49] ram_dat a[59] test_mo de[0] jtag_td o cpu_add r[4] cpu_add r[9] cpu_add r[16] cpu_add r[22] cpu_clk cpu_dre q0 ic cpu_dat a[10] cpu_dat a[16] cpu_dat a[21] cpu_dat a[27] m2_txd[1 ] m2_txen m2_rxd[2 ] m2_rxer m2_crs m0_activ e_led ram_dat a[34] ram_dat a[36] ram_dat a[41] ram_dat a[47] ram_dat a[53] ram_dat a[58] ram_dat a[63] jtag_tc k ic-gnd cpu_add r[7] cpu_add r[11] cpu_add r[17] cpu_add r[21] cpu_we cpu_sda ck2 cpu_ire q1 cpu_dat a[3] cpu_dat a[6] cpu_dat a[14] cpu_dat a[20] cpu_dat a[24] cpu_dat a[29] m2_txd[2 ] m2_rxd[0 ] m2_rxd[3 ] m2_txcl k ram_dat a[35] ram_dat a[40] ram_dat a[48] ram_dat a[54] ram_dat a[57] ram_dat a[62] jtag_tr st ic_gnd cpu_add r[3] cpu_add r[8] cpu_add r[13] cpu_add r[18] cpu_add r[20] cpu_oe cpu_ts_ ale cpu_dre q1 ic cpu_dat a[4] cpu_dat a[9] cpu_dat a[13] cpu_dat a[18] cpu_dat a[25] cpu_dat a[28] m2_txd[0 ] m2_txd[3 ] m2_col gnd ram_dat a[50] ram_dat a[55] ram_dat a[56] ram_dat a[61] test_mo de[2] jtag_tdi ic_gnd cpu_add r[5] cpu_add r[10] cpu_add r[15] cpu_add r[19] gnd cpu_cs cpu_sda ck1 ic_vdd_i o cpu_ire q0 cpu_dat a[0] cpu_dat a[5] cpu_dat a[2] cpu_dat a[11] cpu_dat a[17] cpu_dat a[19] cpu_dat a[26] cpu_dat a[31] gnd 1 2 3 4 5 6 7 8 91011121314151617181920212223242526 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af vdd_cor e vdd_io zl50110/11/12/14 data sheet 16 zarlink semiconductor inc. zl50112 package view from top side. note that ball a1 is non-chamfered corner. figure 3 - zl50112 package view and ball positions a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af gnd tdm_sto[ 1] tdm_clk o[3] tdm_sto[ 4] tdm_sto[ 5] tdm_sti[ 6] tdm_sto[ 7] tdm_sti[ 7] tdm_clk o[10] tdm_clki [10] tdm_clki [11] tdm_clk o[13] gnd tdm_sto[ 13] tdm_sto[ 14] tdm_clk o[15] n/c aux1_cl ko[0] n/c n/c n/c n/c n/c n/c n/c gnd 1 2 3 4 5 6 7 8 91011121314151617181920212223242526 tdm_frm o_ref tdm_sto[ 0] tdm_sti[ 2] tdm_clki [3] tdm_sti[ 4] tdm_clk o[6] tdm_sto[ 6] tdm_clk o[8] tdm_clki [9] tdm_sto[ 10] tdm_sti[ 10] tdm_clki [12] tdm_sto[ 12] tdm_sti[ 13] tdm_clki [15] tdm_sti[ 15] n/c aux1_cl ki[0] n/c n/c n/c n/c n/c n/c n/c n/c tdm_clki p tdm_frm i_ref tdm_clki _ref tdm_clk o[1] tdm_sti[ 3] tdm_clk o[2] tdm_clki [6] tdm_clki [7] tdm_clk o[9] tdm_sto[ 9] tdm_sti[ 9] tdm_sti[ 11] tdm_clki [13] tdm_clk o[14] aux2_cl ko[0] n/c aux2_cl ko[1] n/c n/c n/c n/c n/c n/c n/c n/c n/c ram_dat a[3] ram_dat a[1] tdm_clki s ram_dat a[0] tdm_sti[ 0] tdm_clki [1] tdm_sto[ 3] tdm_sti[ 5] tdm_clki [5] tdm_clk o[7] tdm_sti[ 8] tdm_clk o[11] tdm_sti[ 12] tdm_sti[ 14] aux2_cl ki[0] aux1_cl ko[1] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c ram_dat a[10] ram_dat a[9] ram_dat a[5] ram_dat a[4] ram_dat a[2] tdm_clk o_ref tdm_clki [0] tdm_clk o[4] tdm_sti[ 1] tdm_clki [4] tdm_sto[ 8] tdm_clki [8] tdm_clk o[12] tdm_sto[ 15] aux2_cl ki[1] aux1_cl ki[1] n/c n/c n/c n/c n/c gnd n/c n/c n/c ic ram_dat a[15] ram_dat a[13] ram_dat a[12] ram_dat a[6] ram_dat a[7] gnd vdd_cor e tdm_sto[ 2] tdm_clk o[0] tdm_clki [2] tdm_clk o[5] vdd_cor e tdm_sto[ 11] tdm_clki [14] n/c n/c n/c n/c vdd_cor e gnd n/c n/c n/c ic m1_linku p_led ram_dat a[21] ram_dat a[18] ram_dat a[16] ram_dat a[14] ram_dat a[11] ram_dat a[8] ic ic m2_linku p_led n/c m1_giga bit_led m_mdio ram_dat a[25] ram_dat a[24] ram_dat a[23] ram_dat a[19] ram_dat a[17] vdd_cor e vdd_cor e m0_giga bit_led m_mdc n/c n/c n/c ram_dat a[29] ram_dat a[28] ram_dat a[27] ram_dat a[26] ram_dat a[22] ram_dat a[20] vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io n/c n/c n/c n/c n/c n/c ram_par ity[1] ram_par ity[0] ram_dat a[31] ram_dat a[30] gnd vdd_cor e vdd_io vdd_cor e gnd n/c n/c n/c n/c ram_par ity[7] ram_par ity[6] ram_par ity[5] ram_par ity[4] ram_par ity[3] ram_par ity[2] vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_rxer m1_txcl k m1_crs n/c n/c n/c ram_add r[5] ram_add r[4] ram_add r[2] ram_add r[3] ram_add r[0] ram_add r[1] vdd_io gnd gnd gnd gnd gnd gnd vdd_io vdd_cor e m1_refc lk m1_rxcl k m1_rxd[5 ] m1_rxd[7 ] m1_rxdv gnd ram_add r[6] ram_add r[7] ram_add r[8] gnd vdd_cor e vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_gtx_ clk gnd m1_txer m1_rxd[2 ] m1_rxd[3 ] gnd ram_add r[9] ram_add r[10] ram_add r[11] ram_add r[13] ram_add r[16] gnd vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_txd[2 ] m1_txd[6 ] m1_txen gnd m1_rxd[4 ] m1_rxd[6 ] ram_add r[12] ram_add r[14] ram_add r[15] ram_add r[19] ic_gnd ic vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_txd[0 ] m1_txd[3 ] m1_txd[5 ] m1_txd[7 ] m1_col m1_rxd[1 ] ram_add r[17] ram_add r[18] ram_bw _b ic_gnd gnd a1vdd vdd_io gnd gnd gnd gnd gnd gnd vdd_io vdd_cor e m1_txd[1 ] m1_txd[4 ] gnd m1_rbc1 m1_rxd[0 ] pll_pri ram_bw _a ram_bw _c ram_rw system_ debug system_ clk vdd_io vdd_io m0_gtx_ clk m0_rxd[2 ] m0_rxd[5 ] m0_txcl k m0_crs m1_rbc0 pll_sec ram_bw _d ram_bw _f system_ rst gpio[2] vdd_cor e vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io m0_txd[7 ] m0_txer m0_txen m0_rxd[4 ] m0_rxdv m0_rxer ram_bw _e ram_bw _g gpio[0] gpio[3] gpio[9] ram_dat a[33] m0_txd[2 ] m0_txd[5 ] m0_txd[6 ] m0_rxd[6 ] m0_rxd[7 ] m0_rxd[3 ] ram_bw _h gpio[4] gpio[6] gpio[10] ram_dat a[32] vdd_cor e vdd_cor e m0_txd[1 ] m0_txd[4 ] m0_rbc0 m0_col m0_rxd[1 ] gpio[1] gpio[7] gpio[8] gpio[15] ram_dat a[39] gnd ram_dat a[45] ram_dat a[52] vdd_cor e jtag_tm s cpu_add r[2] cpu_add r[12] vdd_cor e vdd_cor e cpu_dat a[8] cpu_dat a[15] cpu_dat a[23] vdd_cor e m2_rxcl k m2_rxdv gnd m0_txd[0 ] m0_txd[3 ] m0_refc lk m0_rbc1 m0_rxd[0 ] gpio[5] gpio[11] gpio[14] ram_dat a[38] ram_dat a[43] ram_dat a[44] ram_dat a[51] ram_dat a[60] test_mo de[1] gnd cpu_add r[6] cpu_add r[14] cpu_add r[23] cpu_ta cpu_dat a[1] cpu_dat a[7] cpu_dat a[12] cpu_dat a[22] cpu_dat a[30] m2_txer m2_rxd[1 ] m0_rxcl k m0_linku p_led m2_activ e_led m1_activ e_led n/c gpio[12] gpio[13] ram_dat a[37] ram_dat a[42] ram_dat a[46] ram_dat a[49] ram_dat a[59] test_mo de[0] jtag_td o cpu_add r[4] cpu_add r[9] cpu_add r[16] cpu_add r[22] cpu_clk cpu_dre q0 ic cpu_dat a[10] cpu_dat a[16] cpu_dat a[21] cpu_dat a[27] m2_txd[1 ] m2_txen m2_rxd[2 ] m2_rxer m2_crs m0_activ e_led ram_dat a[34] ram_dat a[36] ram_dat a[41] ram_dat a[47] ram_dat a[53] ram_dat a[58] ram_dat a[63] jtag_tc k ic-gnd cpu_add r[7] cpu_add r[11] cpu_add r[17] cpu_add r[21] cpu_we cpu_sda ck2 cpu_ire q1 cpu_dat a[3] cpu_dat a[6] cpu_dat a[14] cpu_dat a[20] cpu_dat a[24] cpu_dat a[29] m2_txd[2 ] m2_rxd[0 ] m2_rxd[3 ] m2_txcl k ram_dat a[35] ram_dat a[40] ram_dat a[48] ram_dat a[54] ram_dat a[57] ram_dat a[62] jtag_tr st ic_gnd cpu_add r[3] cpu_add r[8] cpu_add r[13] cpu_add r[18] cpu_add r[20] cpu_oe cpu_ts_ ale cpu_dre q1 ic cpu_dat a[4] cpu_dat a[9] cpu_dat a[13] cpu_dat a[18] cpu_dat a[25] cpu_dat a[28] m2_txd[0 ] m2_txd[3 ] m2_col gnd ram_dat a[50] ram_dat a[55] ram_dat a[56] ram_dat a[61] test_mo de[2] jtag_tdi ic_gnd cpu_add r[5] cpu_add r[10] cpu_add r[15] cpu_add r[19] gnd cpu_cs cpu_sda ck1 ic_vdd_i o cpu_ire q0 cpu_dat a[0] cpu_dat a[5] cpu_dat a[2] cpu_dat a[11] cpu_dat a[17] cpu_dat a[19] cpu_dat a[26] cpu_dat a[31] gnd 1 2 3 4 5 6 7 8 91011121314151617181920212223242526 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af vdd_cor e vdd_io zl50110/11/12/14 data sheet 17 zarlink semiconductor inc. zl50110 package view from top side. note that ball a1 is non-chamfered corner. figure 4 - zl50110 package view and ball positions a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af gnd tdm_sto [1] tdm_cl ko[3] tdm_sto [4] tdm_sto [5] tdm_sti[ 6] tdm_sto [7] tdm_sti[ 7] n/c n/c n/c n/c gnd n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 tdm_fr mo_ref tdm_sto [0] tdm_sti[ 2] tdm_cl ki[3] tdm_sti[ 4] tdm_cl ko[6] tdm_sto [6] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c tdm_cl kip tdm_fr mi_ref tdm_cl ki_ref tdm_cl ko[1] tdm_sti[ 3] tdm_cl ko[2] tdm_cl ki[6] tdm_cl ki[7] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c ram_da ta[3] ram_da ta[1] tdm_cl kis ram_da ta[0] tdm_sti[ 0] tdm_cl ki[1] tdm_sto [3] tdm_sti[ 5] tdm_cl ki[5] tdm_cl ko[7] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c ram_da ta[10] ram_da ta[9] ram_da ta[5] ram_da ta[4] ram_da ta[2] tdm_cl ko_ref tdm_cl ki[0] tdm_cl ko[4] tdm_sti[ 1] tdm_cl ki[4] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c gnd n/c n/c n/c n/c ram_da ta[15] ram_da ta[13] ram_da ta [12] ram_da ta[6] ram_da ta[7] gnd vdd_co re tdm_sto [2] tdm_cl ko[0] tdm_cl ki[2] tdm_cl ko[5] vdd_co re n/c n/c n/c n/c n/c n/c vdd_co re gnd n/c n/c n/c n/c n/c ram_da ta[21] ram_da ta[18] ram_da ta [16] ram_da ta[14] ram_da ta[11] ram_da ta[8] n/c n/c m1_link up_led m0_link up_led m1_giga bit_led m_mdio ram_da ta[25] ram_da ta[24] ram_da ta [23] ram_da ta[19] ram_da ta[17] vdd_co re vdd_co re m0_giga bit_led m_mdc n/c n/c n/c ram_da ta[29] ram_da ta[28] ram_da ta [27] ram_da ta[26] ram_da ta[22] ram_da ta[20] vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io n/c n/c n/c n/c n/c n/c ram_pa rity[1] ram_pa rity[0] ram_da ta [31] ram_da ta[30] gnd vdd_co re vdd_io vdd_co re gnd n/c n/c n/c n/c ram_pa rity[7] ram_pa rity[6] ram_pa rity[5] ram_pa rity[4] ram_pa rity[3] ram_pa rity[2] vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_rxe r m1_txcl k m1_crs n/c n/c n/c ram_ad dr[5] ram_ad dr[4] ram_ad dr[2] ram_ad dr[3] ram_ad dr[0] ram_ad dr[1] vdd_io gnd gnd gnd gnd gnd gnd vdd_io vdd_co re m1_ref clk m1_rxcl k m1_rxd[ 5] m1_rxd[ 7] m1_rxd v gnd ram_ad dr[6] ram_ad dr[7] ram_ad dr[8] gnd vdd_co re vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_gtx_ clk gnd m1_txer m1_rxd[ 2] m1_rxd[ 3] gnd ram_ad dr[9] ram_ad dr[10] ram_ad dr[11] ram_ad dr[13] ram_ad dr[16] gnd vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_txd[ 2] m1_txd[ 6] m1_txen gnd m1_rxd[ 4] m1_rxd[ 6] ram_ad dr[12] ram_ad dr[14] ram_ad dr[15] ram_ad dr[19] ic_gnd ic vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_txd[ 0] m1_txd[ 3] m1_txd[ 5] m1_txd[ 7] m1_col m1_rxd[ 1] ram_ad dr[17] ram_ad dr[18] ram_bw _b ic_gnd gnd a1vdd vdd_io gnd gnd gnd gnd gnd gnd vdd_io vdd_co re m1_txd[ 1] m1_txd[ 4] gnd m1_rbc1 m1_rxd[ 0] pll_pri ram_bw _a ram_bw _c ram_rw system _debug system _clk vdd_io vdd_io m0_gtx_ clk m0_rxd[ 2] m0_rxd[ 5] m0_txcl k m0_crs m1_rbc0 pll_sec ram_bw _d ram_bw _f system _rst gpio[2] vdd_co re vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io m0_txd[ 7] m0_txer m0_txen m0_rxd[ 4] m0_rxd v m0_rxe r ram_bw _e ram_bw _g gpio[0] gpio[3] gpio[9] ram_da ta[33] m0_txd[ 2] m0_txd[ 5] m0_txd[ 6] m0_rxd[ 6] m0_rxd[ 7] m0_rxd[ 3] ram_bw _h gpio[4] gpio[6] gpio[10] ram_da ta[32] vdd_co re vdd_co re m0_txd[ 1] m0_txd[ 4] m0_rbc0 m0_col m0_rxd[ 1] gpio[1] gpio[7] gpio[8] gpio[15] ram_da ta[39] gnd ram_da ta [45] ram_da ta[52] vdd_co re jtag_tm s cpu_ad dr[2] cpu_ad dr[12] vdd_co re vdd_co re cpu_dat a[8] cpu_dat a[15] cpu_dat a[23] vdd_co re n/c n/c gnd m0_txd[ 0] m0_txd[ 3] m0_ref clk m0_rbc1 m0_rxd[ 0] gpio[5] gpio[11] gpio[14] ram_da ta[38] ram_da ta[43] ram_da ta[44] ram_da ta [51] ram_da ta[60] test_m ode[1] gnd cpu_ad dr[6] cpu_ad dr[14] cpu_ad dr[23] cpu_ta cpu_dat a[1] cpu_dat a[7] cpu_dat a[12] cpu_dat a[22] cpu_dat a[30] n/c n/c m0_rxcl k n/c n/c m1_acti ve_led n/c gpio[12] gpio[13] ram_da ta [37] ram_da ta[42] ram_da ta[46] ram_da ta[49] ram_da ta [59] test_m ode[0] jtag_td o cpu_ad dr[4] cpu_ad dr[9] cpu_ad dr[16] cpu_ad dr[22] cpu_clk cpu_dr eq0 ic cpu_dat a[10] cpu_dat a[16] cpu_dat a[21] cpu_dat a[27] n/c n/c n/c n/c n/c m0_acti ve_led ram_da ta[34] ram_da ta[36] ram_da ta [41] ram_da ta[47] ram_da ta[53] ram_da ta[58] ram_da ta [63] jtag_tc k ic_gnd cpu_ad dr[7] cpu_ad dr[11] cpu_ad dr[17] cpu_ad dr[21] cpu_we cpu_sd ack2 cpu_ire q1 cpu_dat a[3] cpu_dat a[6] cpu_dat a[14] cpu_dat a[20] cpu_dat a[24] cpu_dat a[29] n/c n/c n/c n/c ram_da ta[35] ram_da ta[40] ram_da ta [48] ram_da ta[54] ram_da ta[57] ram_da ta[62] jtag_tr st ic_gnd cpu_ad dr[3] cpu_ad dr[8] cpu_ad dr[13] cpu_ad dr[18] cpu_ad dr[20] cpu_oe cpu_ts_ ale cpu_dr eq1 ic cpu_dat a[4] cpu_dat a[9] cpu_dat a[13] cpu_dat a[18] cpu_dat a[25] cpu_dat a[28] n/c n/c n/c gnd ram_da ta[50] ram_da ta [55] ram_da ta[56] ram_da ta[61] test_m ode[2] jtag_tdi ic_gnd cpu_ad dr[5] cpu_ad dr[10] cpu_ad dr[15] cpu_ad dr[19] gnd cpu_cs cpu_sd ack1 ic_vdd_i o cpu_ire q0 cpu_dat a[0] cpu_dat a[5] cpu_dat a[2] cpu_dat a[11] cpu_dat a[17] cpu_dat a[19] cpu_dat a[26] cpu_dat a[31] gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af vdd_co re vdd_io zl50110/11/12/14 data sheet 18 zarlink semiconductor inc. zl50114 package view from top side. note that ball a1 is non-chamfered corner. figure 5 - zl50114 package view and ball positions a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af gnd tdm_sto [1] tdm_cl ko[3] n/c n/c n/c n/c n/c n/c n/c n/c n/c gnd n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 tdm_fr mo_ref tdm_sto [0] tdm_sti[ 2] tdm_cl ki[3] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c tdm_cl kip tdm_fr mi_ref tdm_cl ki_ref tdm_cl ko[1] tdm_sti[ 3] tdm_cl ko[2] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c ram_da ta[3] ram_da ta[1] tdm_cl kis ram_da ta[0] tdm_sti[ 0] tdm_cl ki[1] tdm_sto [3] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c ram_da ta[10] ram_da ta[9] ram_da ta[5] ram_da ta[4] ram_da ta[2] tdm_cl ko_ref tdm_cl ki[0] n/c tdm_sti[ 1] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c gnd n/c n/c n/c n/c ram_da ta[15] ram_da ta[13] ram_da ta [12] ram_da ta[6] ram_da ta[7] gnd vdd_co re tdm_sto [2] tdm_cl ko[0] tdm_cl ki[2] n/c vdd_co re n/c n/c n/c n/c n/c n/c vdd_co re gnd n/c n/c n/c n/c n/c ram_da ta[21] ram_da ta[18] ram_da ta [16] ram_da ta[14] ram_da ta[11] ram_da ta[8] n/c n/c m1_link up_led m0_link up_led m1_giga bit_led m_mdio ram_da ta[25] ram_da ta[24] ram_da ta [23] ram_da ta[19] ram_da ta[17] vdd_co re vdd_co re m0_giga bit_led m_mdc n/c n/c n/c ram_da ta[29] ram_da ta[28] ram_da ta [27] ram_da ta[26] ram_da ta[22] ram_da ta[20] vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io n/c n/c n/c n/c n/c n/c ram_pa rity[1] ram_pa rity[0] ram_da ta [31] ram_da ta[30] gnd vdd_co re vdd_io vdd_co re gnd n/c n/c n/c n/c ram_pa rity[7] ram_pa rity[6] ram_pa rity[5] ram_pa rity[4] ram_pa rity[3] ram_pa rity[2] vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_rxe r m1_txcl k m1_crs n/c n/c n/c ram_ad dr[5] ram_ad dr[4] ram_ad dr[2] ram_ad dr[3] ram_ad dr[0] ram_ad dr[1] vdd_io gnd gnd gnd gnd gnd gnd vdd_io vdd_co re m1_ref clk m1_rxcl k m1_rxd[ 5] m1_rxd[ 7] m1_rxd v gnd ram_ad dr[6] ram_ad dr[7] ram_ad dr[8] gnd vdd_co re vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_gtx_ clk gnd m1_txer m1_rxd[ 2] m1_rxd[ 3] gnd ram_ad dr[9] ram_ad dr[10] ram_ad dr[11] ram_ad dr[13] ram_ad dr[16] gnd vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_txd[ 2] m1_txd[ 6] m1_txen gnd m1_rxd[ 4] m1_rxd[ 6] ram_ad dr[12] ram_ad dr[14] ram_ad dr[15] ram_ad dr[19] ic_gnd ic vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_txd[ 0] m1_txd[ 3] m1_txd[ 5] m1_txd[ 7] m1_col m1_rxd[ 1] ram_ad dr[17] ram_ad dr[18] ram_bw _b ic_gnd gnd a1vdd vdd_io gnd gnd gnd gnd gnd gnd vdd_io vdd_co re m1_txd[ 1] m1_txd[ 4] gnd m1_rbc1 m1_rxd[ 0] pll_pri ram_bw _a ram_bw _c ram_rw system _debug system _clk vdd_io vdd_io m0_gtx_ clk m0_rxd[ 2] m0_rxd[ 5] m0_txcl k m0_crs m1_rbc0 pll_sec ram_bw _d ram_bw _f system _rst gpio[2] vdd_co re vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io m0_txd[ 7] m0_txer m0_txen m0_rxd[ 4] m0_rxd v m0_rxe r ram_bw _e ram_bw _g gpio[0] gpio[3] gpio[9] ram_da ta[33] m0_txd[ 2] m0_txd[ 5] m0_txd[ 6] m0_rxd[ 6] m0_rxd[ 7] m0_rxd[ 3] ram_bw _h gpio[4] gpio[6] gpio[10] ram_da ta[32] vdd_co re vdd_co re m0_txd[ 1] m0_txd[ 4] m0_rbc0 m0_col m0_rxd[ 1] gpio[1] gpio[7] gpio[8] gpio[15] ram_da ta[39] gnd ram_da ta [45] ram_da ta[52] vdd_co re jtag_tm s cpu_ad dr[2] cpu_ad dr[12] vdd_co re vdd_co re cpu_dat a[8] cpu_dat a[15] cpu_dat a[23] vdd_co re n/c n/c gnd m0_txd[ 0] m0_txd[ 3] m0_ref clk m0_rbc1 m0_rxd[ 0] gpio[5] gpio[11] gpio[14] ram_da ta[38] ram_da ta[43] ram_da ta[44] ram_da ta [51] ram_da ta[60] test_m ode[1] gnd cpu_ad dr[6] cpu_ad dr[14] cpu_ad dr[23] cpu_ta cpu_dat a[1] cpu_dat a[7] cpu_dat a[12] cpu_dat a[22] cpu_dat a[30] n/c n/c m0_rxcl k n/c n/c m1_acti ve_led n/c gpio[12] gpio[13] ram_da ta [37] ram_da ta[42] ram_da ta[46] ram_da ta[49] ram_da ta [59] test_m ode[0] jtag_td o cpu_ad dr[4] cpu_ad dr[9] cpu_ad dr[16] cpu_ad dr[22] cpu_clk cpu_dr eq0 ic cpu_dat a[10] cpu_dat a[16] cpu_dat a[21] cpu_dat a[27] n/c n/c n/c n/c n/c m0_acti ve_led ram_da ta[34] ram_da ta[36] ram_da ta [41] ram_da ta[47] ram_da ta[53] ram_da ta[58] ram_da ta [63] jtag_tc k ic_gnd cpu_ad dr[7] cpu_ad dr[11] cpu_ad dr[17] cpu_ad dr[21] cpu_we cpu_sd ack2 cpu_ire q1 cpu_dat a[3] cpu_dat a[6] cpu_dat a[14] cpu_dat a[20] cpu_dat a[24] cpu_dat a[29] n/c n/c n/c n/c ram_da ta[35] ram_da ta[40] ram_da ta [48] ram_da ta[54] ram_da ta[57] ram_da ta[62] jtag_tr st ic_gnd cpu_ad dr[3] cpu_ad dr[8] cpu_ad dr[13] cpu_ad dr[18] cpu_ad dr[20] cpu_oe cpu_ts_ ale cpu_dr eq1 ic cpu_dat a[4] cpu_dat a[9] cpu_dat a[13] cpu_dat a[18] cpu_dat a[25] cpu_dat a[28] n/c n/c n/c gnd ram_da ta[50] ram_da ta [55] ram_da ta[56] ram_da ta[61] test_m ode[2] jtag_tdi ic_gnd cpu_ad dr[5] cpu_ad dr[10] cpu_ad dr[15] cpu_ad dr[19] gnd cpu_cs cpu_sd ack1 ic_vdd_i o cpu_ire q0 cpu_dat a[0] cpu_dat a[5] cpu_dat a[2] cpu_dat a[11] cpu_dat a[17] cpu_dat a[19] cpu_dat a[26] cpu_dat a[31] gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af vdd_co re vdd_io zl50110/11/12/14 data sheet 19 zarlink semiconductor inc. ball signal assignment ball number signal name a1 gnd a2 tdm_sto[1] a3 tdm_clko[3] a4 ? tdm_sto[4] a5 ? tdm_sto[5] a6 ? tdm_sti[6] a7 ? tdm_sto[7] a8 ? tdm_sti[7] a9 ? tdm_clko[10] a10 ? tdm_clki[10] a11 ? tdm_clki[11] a12 ? tdm_clko[13] a13 gnd a14 ? tdm_sto[13] a15 ? tdm_sto[14] a16 ? tdm_clko[15] a17 * tdm_sto[16] a18 ?* tdm_clko[18] a19 * tdm_sti[18] a20 * tdm_clki[20] a21 * tdm_sti[20] a22 * tdm_sto[21] a23 * tdm_sti[21] a24 * tdm_clko[24] a25 * tdm_clko[25] a26 gnd b1 tdm_frmo_ref b2 tdm_sto[0] b3 tdm_sti[2] b4 tdm_clki[3] b5 ? tdm_sti[4] b6 ? tdm_clko[6] b7 ? tdm_sto[6] b8 ? tdm_clko[8] b9 ? tdm_clki[9] b10 ? tdm_sto[10] b11 ? tdm_sti[10] b12 ? tdm_clki[12] b13 ? tdm_sto[12] b14 ? tdm_sti[13] b15 ? tdm_clki[15] b16 ? tdm_sti[15] b17 * tdm_sti[17] b18 ?* tdm_clki[18] b19 * tdm_clko[20] b20 * tdm_sto[19] b21 * tdm_sto[22] b22 * tdm_clko[23] b23 * tdm_sto[24] b24 * tdm_clko[26] b25 * tdm_sti[24] b26 * tdm_clko[27] c1 tdm_clkip c2 tdm_frmi_ref c3 tdm_clki_ref c4 tdm_clko[1] c5 tdm_sti[3] c6 tdm_clko[2] c7 ? tdm_clki[6] c8 ? tdm_clki[7] c9 ? tdm_clko[9] c10 ? tdm_sto[9] c11 ? tdm_sti[9] c12 ? tdm_sti[11] c13 ? tdm_clki[13] c14 ? tdm_clko[14] c15 * tdm_clko[16] c16 * tdm_sti[16] c17 * tdm_clko[17] c18 * tdm_sti[19] c19 * tdm_clko[21] c20 * tdm_clki[21] c21 * tdm_clki[24] c22 * tdm_sti[22] c23 * tdm_sto[26] ball number signal name c24 * tdm_clki[27] c25 * tdm_sti[27] c26 * tdm_sti[28] d1 ram_data[3] d2 ram_data[1] d3 tdm_clkis d4 ram_data[0] d5 tdm_sti[0] d6 tdm_clki[1] d7 tdm_sto[3] d8 ? tdm_sti[5] d9 ? tdm_clki[5] d10 ? tdm_clko[7] d11 ? tdm_sti[8] d12 ? tdm_clko[11] d13 ? tdm_sti[12] d14 ? tdm_sti[14] d15 ?* tdm_clki[16] d16 ? tdm_clko[19] d17 * tdm_sto[18] d18 * tdm_sto[20] d19 * tdm_clko[22] d20 * tdm_sto[27] d21 * tdm_sto[25] d22 * tdm_clki[26] d23 * tdm_clko[28] d24 * tdm_clki[29] d25 * tdm_sti[29] d26 * tdm_sti[31] e1 ram_data[10] e2 ram_data[9] e3 ram_data[5] e4 ram_data[4] e5 ram_data[2] e6 tdm_clko_ref e7 tdm_clki[0] e8 ? tdm_clko[4] e9 tdm_sti[1] ball number signal name zl50110/11/12/14 data sheet 20 zarlink semiconductor inc. e10 ? tdm_clki[4] e11 ? tdm_sto[8] e12 ? tdm_clki[8] e13 ? tdm_clko[12] e14 ? tdm_sto[15] e15 * tdm_clki[17] e16 * tdm_clki[19] e17 * tdm_sto[23] e18 * tdm_sti[23] e19 * tdm_clki[25] e20 * tdm_sti[26] e21 * tdm_clki[28] e22 gnd e23 * tdm_clko[30] e24 * tdm_clki[30] e25 * tdm_sti[30] e26 ?* tdm_sto[29] f1 ram_data[15] f2 ram_data[13] f3 ram_data[12] f4 ram_data[6] f5 ram_data[7] f6 gnd f7 vdd_core f8 tdm_sto[2] f9 tdm_clko[0] f10 tdm_clki[2] f11 ? tdm_clko[5] f12 vdd_core f13 ? tdm_sto[11] f14 ? tdm_clki[14] f15 vdd_core f16 * tdm_sto[17] f17 * tdm_clki[22] f18 * tdm_sti[25] f19 * tdm_clki[23] f20 vdd_core f21 gnd ball number signal name f22 * tdm_clki[31] f23 * tdm_clko[29] f24 * tdm_sto[28] f25 * tdm_clko[31] f26 ? m1_linkup_led g1 ram_data[21] g2 ram_data[18] g3 ram_data[16] g4 ram_data[14] g5 ram_data[11] g6 ram_data[8] g21 * tdm_sto[31] g22 * tdm_sto[30] g23 m1/2_linkup_led g24 m0/3_linkup_led g25 m1_gigabit_led g26 m_mdio h1 ram_data[25] h2 ram_data[24] h3 ram_data[23] h4 ram_data[19] h5 ram_data[17] h6 vdd_core h21 vdd_core h22 m0_gigabit_led h23 m_mdc h24 * m3_crs h25 * m3_txclk h26 * m3_rxer j1 ram_data[29] j2 ram_data[28] j3 ram_data[27] j4 ram_data[26] j5 ram_data[22] j6 ram_data[20] j9 vdd_io j10 vdd_io j11 vdd_io ball number signal name j12 vdd_io j13 vdd_io j14 vdd_io j15 vdd_io j16 vdd_io j17 vdd_io j18 vdd_io j21 * m3_rxdv j22 * m3_rxd[3] j23 * m3_rxd[2] j24 * m3_rxd[1] j25 * m3_rxd[0] j26 * m3_col k1 ram_parity[1] k2 ram_parity[0] k3 ram_data[31] k4 ram_data[30] k5 gnd k6 vdd_core k9 vdd_io k18 vdd_io k21 vdd_core k22 gnd k23 * m3_txd[3] k24 * m3_txen k25 * m3_txer k26 * m3_rxclk l1 ram_parity[7] l2 ram_parity[6] l3 ram_parity[5] l4 ram_parity[4] l5 ram_parity[3] l6 ram_parity[2] l9 vdd_io l11 gnd l12 gnd l13 gnd l14 gnd ball number signal name zl50110/11/12/14 data sheet 21 zarlink semiconductor inc. l15 gnd l16 gnd l18 vdd_io l21 m1_rxer l22 m1_txclk l23 m1_crs l24 * m3_txd[0] l25 * m3_txd[1] l26 * m3_txd[2] m1 ram_addr[5] m2 ram_addr[4] m3 ram_addr[2] m4 ram_addr[3] m5 ram_addr[0] m6 ram_addr[1] m9 vdd_io m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m16 gnd m18 vdd_io m21 vdd_core m22 m1_refclk m23 m1_rxclk m24 m1_rxd[5] m25 m1_rxd[7] m26 m1_rxdv n1 gnd n2 ram_addr[6] n3 ram_addr[7] n4 ram_addr[8] n5 gnd n6 vdd_core n9 vdd_io n11 gnd n12 gnd ball number signal name n13 gnd n14 gnd n15 gnd n16 gnd n18 vdd_io n21 m1_gtx_clk n22 gnd n23 m1_txer n24 m1_rxd[2] n25 m1_rxd[3] n26 gnd p1 ram_addr[9] p2 ram_addr[10] p3 ram_addr[11] p4 ram_addr[13] p5 ram_addr[16] p6 gnd p9 vdd_io p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd p16 gnd p18 vdd_io p21 m1_txd[2] p22 m1_txd[6] p23 m1_txen p24 gnd p25 m1_rxd[4] p26 m1_rxd[6] r1 ram_addr[12] r2 ram_addr[14] r3 ram_addr[15] r4 ram_addr[19] r5 ic_gnd r6 ic r9 vdd_io ball number signal name r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd r18 vdd_io r21 m1_txd[0] r22 m1_txd[3] r23 m1_txd[5] r24 m1_txd[7] r25 m1_col r26 m1_rxd[1] t1 ram_addr[17] t2 ram_addr[18] t3 ram_bw_b t4 ic_gnd t5 gnd t6 a1vdd t9 vdd_io t11 gnd t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd t18 vdd_io t21 vdd_core t22 m1_txd[1] t23 m1_txd[4] t24 gnd t25 m1_rbc1 t26 m1_rxd[0] u1 pll_pri u2 ram_bw_a u3 ram_bw_c u4 ram_rw u5 system_debug ball number signal name zl50110/11/12/14 data sheet 22 zarlink semiconductor inc. u6 system_clk u9 vdd_io u18 vdd_io u21 m0_gtx_clk u22 m0_rxd[2] u23 m0_rxd[5] u24 m0_txclk u25 m0_crs u26 m1_rbc0 v1 pll_sec v2 ram_bw_d v3 ram_bw_f v4 system_rst v5 gpio[2] v6 vdd_core v9 vdd_io v10 vdd_io v11 vdd_io v12 vdd_io v13 vdd_io v14 vdd_io v15 vdd_io v16 vdd_io v17 vdd_io v18 vdd_io v21 m0_txd[7] v22 m0_txer v23 m0_txen v24 m0_rxd[4] v25 m0_rxdv v26 m0_rxer w1 ram_bw_e w2 ram_bw_g w3 gpio[0] w4 gpio[3] w5 gpio[9] w6 ram_data[33] w21 m0_txd[2] ball number signal name w22 m0_txd[5] w23 m0_txd[6] w24 m0_rxd[6] w25 m0_rxd[7] w26 m0_rxd[3] y1 ram_bw_h y2 gpio[4] y3 gpio[6] y4 gpio[10] y5 ram_data[32] y6 vdd_core y21 vdd_core y22 m0_txd[1] y23 m0_txd[4] y24 m0_rbc0 y25 m0_col y26 m0_rxd[1] aa1 gpio[1] aa2 gpio[7] aa3 gpio[8] aa4 gpio[15] aa5 ram_data[39] aa6 gnd aa7 ram_data[45] aa8 ram_data[52] aa9 vdd_core aa10 jtag_tms aa11 cpu_addr[2] aa12 cpu_addr[12] aa13 vdd_core aa14 vdd_core aa15 cpu_data[8] aa16 cpu_data[15] aa17 cpu_data[23] aa18 vdd_core aa19 ? m2_rxclk aa20 ? m2_rxdv aa21 gnd ball number signal name aa22 m0_txd[0] aa23 m0_txd[3] aa24 m0_refclk aa25 m0_rbc1 aa26 m0_rxd[0] ab1 gpio[5] ab2 gpio[11] ab3 gpio[14] ab4 ram_data[38] ab5 ram_data[43] ab6 ram_data[44] ab7 ram_data[51] ab8 ram_data[60] ab9 test_mode[1] ab10 gnd ab11 cpu_addr[6] ab12 cpu_addr[14] ab13 cpu_addr[23] ab14 cpu_ta ab15 cpu_data[1] ab16 cpu_data[7] ab17 cpu_data[12] ab18 cpu_data[22] ab19 cpu_data[30] ab20 ? m2_txer ab21 ? m2_rxd[1] ab22 m0_rxclk ab23 ? m0_linkup_led ab24 ? m2_active_led ab25 m1_active_led ab26 * m3_active_led ac1 gpio[12] ac2 gpio[13] ac3 ram_data[37] ac4 ram_data[42] ac5 ram_data[46] ac6 ram_data[49] ac7 ram_data[59] ball number signal name zl50110/11/12/14 data sheet 23 zarlink semiconductor inc. * not connected on zl50112, zl50110 and zl50114 - leave open circuit. ? not connected on zl50110 and zl50114 - leave open circuit. ? not connected on zl50114 - leave open circuit. n/c - not connected - leave open circuit. * internally connected on zl50112 - leave open circuit. ic - internally connected - leave open circuit. ic_gnd - tie to ground ic_vdd_io - tie to vdd_io ac8 test_mode[0] ac9 jtag_tdo ac10 cpu_addr[4] ac11 cpu_addr[9] ac12 cpu_addr[16] ac13 cpu_addr[22] ac14 cpu_clk ac15 cpu_dreq0 ac16 ic ac17 cpu_data[10] ac18 cpu_data[16] ac19 cpu_data[21] ac20 cpu_data[27] ac21 ? m2_txd[1] ac22 ? m2_txen ac23 ? m2_rxd[2] ac24 ? m2_rxer ac25 ? m2_crs ac26 m0_active_led ad1 ram_data[34] ad2 ram_data[36] ad3 ram_data[41] ad4 ram_data[47] ad5 ram_data[53] ad6 ram_data[58] ad7 ram_data[63] ad8 jtag_tck ad9 ic_gnd ad10 cpu_addr[7] ad11 cpu_addr[11] ad12 cpu_addr[17] ad13 cpu_addr[21] ad14 cpu_we ad15 cpu_sdack2 ad16 cpu_ireq1 ad17 cpu_data[3] ad18 cpu_data[6] ad19 cpu_data[14] ball number signal name ad20 cpu_data[20] ad21 cpu_data[24] ad22 cpu_data[29] ad23 ? m2_txd[2] ad24 ? m2_rxd[0] ad25 ? m2_rxd[3] ad26 ? m2_txclk ae1 ram_data[35] ae2 ram_data[40] ae3 ram_data[48] ae4 ram_data[54] ae5 ram_data[57] ae6 ram_data[62] ae7 jtag_trst ae8 ic_gnd ae9 cpu_addr[3] ae10 cpu_addr[8] ae11 cpu_addr[13] ae12 cpu_addr[18] ae13 cpu_addr[20] ae14 cpu_oe ae15 cpu_ts_ale ae16 cpu_dreq1 ae17 ic ae18 cpu_data[4] ae19 cpu_data[9] ae20 cpu_data[13] ae21 cpu_data[18] ae22 cpu_data[25] ae23 cpu_data[28] ae24 ? m2_txd[0] ae25 ? m2_txd[3] ae26 ? m2_col af1 gnd af2 ram_data[50] af3 ram_data[55] af4 ram_data[56] af5 ram_data[61] ball number signal name af6 test_mode[2] af7 jtag_tdi af8 ic_gnd af9 cpu_addr[5] af10 cpu_addr[10] af11 cpu_addr[15] af12 cpu_addr[19] af13 gnd af14 cpu_cs af15 cpu_sdack1 af16 ic_vdd_io af17 cpu_ireq0 af18 cpu_data[0] af19 cpu_data[5] af20 cpu_data[2] af21 cpu_data[11] af22 cpu_data[17] af23 cpu_data[19] af24 cpu_data[26] af25 cpu_data[31] af26 gnd ball number signal name zl50110/11/12/14 data sheet 24 zarlink semiconductor inc. 3.0 external interface description the following key applies to all tables: 3.1 tdm interface all tdm interface signals are 5 v tolerant. all tdm interface inputs (including data, clock and frame pul se) have internal pull-down resistors so they can be safely left unconnected if not used. 3.1.1 zl50111 variant tdm stream connection i input ooutput d internal 100 k pull-down resistor present u internal 100 k pull-up resistor present t tri-state output signal i/o package balls description tdm_sti[31:0] i d [31] d26 [15] b16 [30] e25 [14] d14 [29] d25 [13] b14 [28] c26 [12] d13 [27] c25 [11] c12 [26] e20 [10] b11 [25] f18 [9] c11 [24] b25 [8] d11 [23] e18 [7] a8 [22] c22 [6] a6 [21] a23 [5] d8 [20] a21 [4] b5 [19] c18 [3] c5 [18] a19 [2] b3 [17] b17 [1] e9 [16] c16 [0] d5 tdm port serial data input streams. for different standards these pins are given different identities: st-bus: tdm_sti[31:0] h.110: tdm_d[31:0] h-mvip: tdm_hds[31:0] triggered on rising edge or falling edge depending on standard. at 8.192 mbps only streams [7:0] are used, with 128 channels per stream. streams [7:0] are used for j2, and streams [1:0] are used for t3 and e3. table 2 - tdm interface zl50111 stream pin definition zl50110/11/12/14 data sheet 25 zarlink semiconductor inc. tdm_sto[31:0] ot [31] g21 [15] e14 [30] g22 [14] a15 [29] e26 [13] a14 [28] f24 [12] b13 [27] d20 [11] f13 [26] c23 [10] b10 [25] d21 [9] c10 [24] b23 [8] e11 [23] e17 [7] a7 [22] b21 [6] b7 [21] a22 [5] a5 [20] d18 [4] a4 [19] b20 [3] d7 [18] d17 [2] f8 [17] f16 [1] a2 [16] a17 [0] b2 tdm port serial data output streams. for different standards these pins are given different identities: st-bus: tdm_sto[31:0] h.110: tdm_d[31:0] h-mvip: tdm_hds[31:0] triggered on rising edge or falling edge depending on standard. at 8.192 mbps only streams [7:0] are used, with 128 channels per stream. streams [7:0] are used for j2, and streams [1:0] are used for t3 and e3. tdm_clki[31:0] i d [31] f22 [15] b15 [30] e24 [14] f14 [29] d24 [13] c13 [28] e21 [12] b12 [27] c24 [11] a11 [26] d22 [10] a10 [25] e19 [9] b9 [24] c21 [8] e12 [23] f19 [7] c8 [22] f17 [6] c7 [21] c20 [5] d9 [20] a20 [4] e10 [19] e16 [3] b4 [18] b18 [2] f10 [17] e15 [1] d6 [16] d15 [0] e7 tdm port clock inputs. programmable as active high or low. can accept frequencies of 1.544 mhz, 2.048 mhz, 4.096 mhz, 6.312 mhz, 8.192 mhz, 16.384 mhz, 34.368 mhz or 44.736 mhz depending on standard used. at 8.192 mbps only streams [7:0] are used. streams [7:0] are used for j2, and streams [1:0] are used for t3 and e3. signal i/o package balls description table 2 - tdm interface zl50111 stream pin definition (continued) zl50110/11/12/14 data sheet 26 zarlink semiconductor inc. note: speed modes: 2.048 mbps - all 32 streams active (bits [31:0]), with 32 channels per stream - 1024 total channels. 8.192 mbps - 8 streams active (bits [7:0]), with 128 channels per stream - 1024 total channels. j2 - 8 streams active (bits [7:0]), with 98 channels per stream - 784 total channels. e3 - 2 streams active (bits [1:0]), with 537 channels per stream - 1074 total channels. t3 - 2 streams active (bits [1:0]), with 699 channels per stream - 1398 total channels. note: all tdm interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely l eft unconnected if not used. 3.1.2 zl50112 variant tdm stream connection tdm_clko[31:0] o [31] f25 [15] a16 [30] e23 [14] c14 [29] f23 [13] a12 [28] d23 [12] e13 [27] b26 [11] d12 [26] b24 [10] a9 [25] a25 [9] c9 [24] a24 [8] b8 [23] b22 [7] d10 [22] d19 [6] b6 [21] c19 [5] f11 [20] b19 [4] e8 [19] d16 [3] a3 [18] a18 [2] c6 [17] c17 [1] c4 [16] c15 [0] f9 tdm port clock outputs. will generate 1.544 mhz, 2.048 mhz, 4.096 mhz, 6.312 mhz, 8.192 mhz, 16.384 mhz, 34.368 mhz or 44.736 mhz depending on standard used. at 8.192 mbps only streams [7:0] are used. streams [7:0] are used for j2, and streams [1:0] are used for t3 and e3. signal i/o package balls description tdm_sti[15:0] i d [15] b16 [14] d14 [13] b14 [12] d13 [11] c12 [10] b11 [9] c11 [8] d11 [7] a8 [6] a6 [5] d8 [4] b5 [3] c5 [2] b3 [1] e9 [0] d5 tdm port serial data input streams. for different standards these pins are given different identities: st-bus: tdm_sti[15:0] h.110: tdm_d[15:0] h-mvip: tdm_hds[15:0] triggered on rising edge or falling edge depending on standard. at 8.192 mbps only streams [3:0] are used, with 128 channels per stream. streams [3:0] are used for j2. table 3 - tdm interface zl50112 stream pin definition signal i/o package balls description table 2 - tdm interface zl50111 stream pin definition (continued) zl50110/11/12/14 data sheet 27 zarlink semiconductor inc. tdm_sto[15:0] ot [15] e14 [14] a15 [13] a14 [12] b13 [11] f13 [10] b10 [9] c10 [8] e11 [7] a7 [6] b7 [5] a5 [4] a4 [3] d7 [2] f8 [1] a2 [0] b2 tdm port serial data output streams. for different standards these pins are given different identities: st-bus: tdm_sto[15:0] h.110: tdm_d[15:0] h-mvip: tdm_hds[15:0] triggered on rising edge or falling edge depending on standard. at 8.192 mbps only streams [3:0] are used, with 128 channels per stream. streams [3:0] are used for j2. tdm_clki[15:0] i d [15] b15 [14] f14 [13] c13 [12] b12 [11] a11 [10] a10 [9] b9 [8] e12 [7] c8 [6] c7 [5] d9 [4] e10 [3] b4 [2] f10 [1] d6 [0] e7 tdm port clock inputs. programmable as active high or low. can accept frequencies of 1.544 mhz, 2.048 mhz, 4.096 mhz, 6.312 mhz, 8.192 mhz, 16.384 mhz, 34.368 mhz or 44.736 mhz depending on standard used. at 8.192 mbps only streams [3:0] are used. streams [3:0] are used for j2. signal i/o package balls description table 3 - tdm interface zl50112 stream pin definition (continued) zl50110/11/12/14 data sheet 28 zarlink semiconductor inc. note: speed modes: 2.048 mbps - all 16 streams active (bits [15:0]), with 32 channels per stream - 512 total channels. 8.192 mbps - 4 streams active (bits [3:0]), with 128 channels per stream - 512 total channels. j2 - 4 streams active (bits [3:0]), with 98 channels per stream - 392 total channels. note: all tdm interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely l eft unconnected if not used. tdm_clko[15:0] o [15] a16 [14] c14 [13] a12 [12] e13 [11] d12 [10] a9 [9] c9 [8] b8 [7] d10 [6] b6 [5] f11 [4] e8 [3] a3 [2] c6 [1] c4 [0] f9 tdm port clock outputs. will generate 1.544 mhz, 2.048 mhz, 4.096 mhz, 6.312 mhz, 8.192 mhz, 16.384 mhz depending on standard used. at 8.192 mbps only streams [3:0] are used. streams [3:0] are used for j2. signal i/o package balls description table 3 - tdm interface zl50112 stream pin definition (continued) zl50110/11/12/14 data sheet 29 zarlink semiconductor inc. 3.1.3 zl50110 variant tdm stream connection note: speed modes: 2.048 mbps - all 8 streams active (bits [7:0]), with 32 channels per stream - 256 total channels. 8.192 mbps - 2 streams active (bits [1:0]), with 128 channels per stream - 256 total channels. j2 - 2 streams active (bits [1:0]), with 98 channels per stream - 196 total channels. note: all tdm interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely l eft unconnected if not used. signal i/o package balls description tdm_sti[7:0] i d [7] a8 [6] a6 [5] d8 [4] b5 [3] c5 [2] b3 [1] e9 [0] d5 tdm port serial data input streams. for different standards these pins are given different identities: st-bus: tdm_sti[7:0] h.110: tdm_d[7:0] h-mvip: tdm_hds[7:0] triggered on rising edge or falling edge depending on standard. at 8.192 mbps only streams [1:0] are used. streams [1:0] are used for j2. tdm_sto[7:0] ot [7] a7 [6] b7 [5] a5 [4] a4 [3] d7 [2] f8 [1] a2 [0] b2 tdm port serial data output streams. for different standards these pins are given different identities: st-bus: tdm_sto[7:0] h.110: tdm_d[7:0] h-mvip: tdm_hds[7:0] triggered on rising edge or falling edge depending on standard. at 8.192 mbps only streams [1:0] are used. streams [1:0] are used for j2. tdm_clki[7:0] i d [7] c8 [6] c7 [5] d9 [4] e10 [3] b4 [2] f10 [1] d6 [0] e7 tdm port clock inputs programmable as active high or low. can accept frequencies of 1.544 mhz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 6.312 mhz or 16.384 mhz depending on standard used. at 8.192 mbps only streams [1:0] are used. streams [1:0] are used for j2. tdm_clko[7:0] o [7] d10 [6] b6 [5] f11 [4] e8 [3] a3 [2] c6 [1] c4 [0] f9 tdm port clock outputs. will generate 1.544 mhz, 2.048 mhz, 4.096 mhz, 6.312 mhz, 8.192 mhz or 16.384 mhz depending on standard used. at 8.192 mbps only streams [1:0] are used. streams [1:0] are used for j2. table 4 - tdm interface zl50110 stream pin definition zl50110/11/12/14 data sheet 30 zarlink semiconductor inc. 3.1.4 zl50114 variant tdm stream connection note: speed modes: 2.048 mbps - all 4 streams active (bits [3:0]), with 32 channels per stream - 128 total channels. 8.192 mbps - 2 streams active (bits [1:0]), with 128 channels per stream - 256 total channels. j2 - 2 streams active (bits [1:0]), with 98 channels per stream - 196 total channels. note: all tdm interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely l eft unconnected if not used. signal i/o package balls description tdm_sti[3:0] i d [3] c5 [2] b3 [1] e9 [0] d5 tdm port serial data input streams. for different standards these pins are given different identities: st-bus: tdm_sti[3:0] h.110: tdm_d[3:0] h-mvip: tdm_hds[3:0] triggered on rising edge or falling edge depending on standard. at 8.192 mbps only streams [1:0] are used. streams [1:0] are used for j2. tdm_sto[3:0] ot [3] d7 [2] f8 [1] a2 [0] b2 tdm port serial data output streams. for different standards these pins are given different identities: st-bus: tdm_sto[3:0] h.110: tdm_d[3:0] h-mvip: tdm_hds[3:0] triggered on rising edge or falling edge depending on standard. at 8.192 mbps only streams [1:0] are used. streams [1:0] are used for j2. tdm_clki[3:0] i d [3] b4 [2] f10 [1] d6 [0] e7 tdm port clock inputs programmable as active high or low. can accept frequencies of 1.544 mhz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 6.312 mhz or 16.384 mhz depending on standard used. at 8.192 mbps only streams [1:0] are used. streams [1:0] are used for j2. tdm_clko[3:0] o [3] a3 [2] c6 [1] c4 [0] f9 tdm port clock output s. will generate 1.544 mhz, 2.048 mhz, 4.096 mhz, 6.312 mhz, 8.192 mhz or 16.384 mhz depending on standard used. at 8.192 mbps only streams [1:0] are used. streams [1:0] are used for j2. table 5 - tdm interface zl50114 stream pin definition zl50110/11/12/14 data sheet 31 zarlink semiconductor inc. 3.1.5 tdm signals common to zl50110, zl50111, zl50112 and zl50114 signal i/o package balls description tdm_clki_ref i d c3 tdm port reference clock input for backplane operation tdm_clko_ref o e6 tdm port reference clock output for backplane operation tdm_frmi_ref i d c2 tdm port reference frame input. for different standards this pin is given a different identity: st-bus: tdm_f0i h.110: tdm_frame h-mvip: tdm_f0 signal is normally active low, but can be active high depending on standard. indicates the start of a tdm frame by pulsing every 125 s. normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. tdm_frmo_ref o b1 tdm port reference frame output. for different standards this pin is given a different identity: st-bus: tdm_f0o h.110: tdm_frame h-mvip: tdm_f0 signal is normally active low, but can be active high depending on standard. indicates the start of a tdm frame by pulsing every 125 s. normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. table 6 - tdm interface common pin definition zl50110/11/12/14 data sheet 32 zarlink semiconductor inc. 3.2 pac interface all pac interface signals are 5 v tolerant all pac interface outputs are high impedance while system reset is low. signal i/o package balls description tdm_clkip i d c1 primary reference clock input. should be driven by external clock source to provide locking reference to internal / optional external dpll in tdm master mode. also provides prs clock for rtp timestamps in synchronous modes. acceptable frequency range: 8 khz - 34.368 mhz (generally should be between 10 mhz and 25 mhz as per itu-t y.1413. tdm_clkis i d d3 secondary reference clock input. backup external reference for automatic switch-over in case of failure of tdm_clkip source. pll_pri ot u1 primary reference output to optional external dpll. multiplexed & frequency divided reference output for support of opt ional external dpll. expected frequency range: 8 khz - 16.384 mhz. pll_sec ot v1 secondary reference output to optional external dpll multiplexed & frequency divided reference output for support of optional external dpll. expected frequency range: 8 khz - 16.384 mhz. table 7 - pac interface package ball definition zl50110/11/12/14 data sheet 33 zarlink semiconductor inc. 3.3 packet interfaces for the zl50111 and zl50112 variants the packet interface is capable of either 3 mii interfaces, 2 redundant gmii interfaces or 2 redundant tbi (1000 mbps) interfaces. the tbi interface is a pcs interface supported by an integrated 1000base-x pcs module. the zl50110 and zl501 14 variants have either 2 mii interfaces, 2 redundant gmii interfaces or 2 redundant tbi (1 000 mbps) interfaces. when the packet interface is programmed for pcs/tbi mode, by default the hardware will not enable auto-n egotiation. the tbi auto-negotiation must be done by application software. ports 2 and 3 are not available on the zl50110 and zl50114 devices. note: in gmii/tbi mode only 1 gmac port may be used to receive data. the second gmac port is for redundancy purposes only. data for all three types of packet switching is based on specification ieee std. 802.3 - 2000. the table below highlights the valid ethernet interface combinations: note: port 2 and port 3 can not be used to receive data si multaneously, they are mutually exclusive for packet reception. they may both be used for packet transmission if required. the zl50110/11/12/14 will not take action when receiv ing a pause frame. it will not pause the transmission of traffic. it is normally not required to st op cesop traffic because it is generally c onstant bit rate and time sensitive. if necessary, the limiting of egress non-cesop traffic may be done external to the zl50110/11/12/14 (e.g. in an ethernet switch). table 8 maps the signal pins used in the mii interface to those used in the gmii and tbi interface. table 9 shows mii management interface package ball de finition. table 10, table 11, table 12, and table 13 show respectively the mii port 0, port 1, port 2 and port 3 interface package ball definition. all packet interface signals are 5 v tolerant, and all outputs are high impedance while system reset is low. mii port 0 mii port 1 mii port 2* mii port 3** ge ge*** -- -- ge -- fe -- ge -- -- fe fe fe -- -- fe fe fe -- fe fe -- fe note 1: *zl50111/112 only note 2: **zl50111 only note 3: ***standby only mii gmii tbi (pcs) m n _linkup_led m n _linkup_led m n _linkup_led m n _active_led m n _active_led m n _active_led -m n _gigabit_led m n _gigabit_led -m n _refclk m n _refclk m n _rxclk m n _rxclk m n _rbc0 table 8 - packet interface signal mapping - mii to gmii/tbi zl50110/11/12/14 data sheet 34 zarlink semiconductor inc. note: m n can be either m0, m1, m2, or m3 for zl50111 and zl50112 variants; and m0 or m1 for zl50110 variant. m n _col m n _col m n _rbc1 m n _rxd[3:0] m n _rxd[7:0] m n _rxd[7:0] m n _rxdv m n _rxdv m n _rxd[8] m n _rxer m n _rxer m n _rxd[9] m n _crs m n _crs m n _signal_detect m n _txclk - - m n _txd[3:0] m n _txd[7:0] m n _txd[7:0] m n _txen m n _txen m n _txd[8] m n _txer m n _txer m n _txd[9] -m n _gtx_clk m n _gtx_clk signal i/o package balls description m_mdc o h23 mii management data clock. common for all four mii ports. it has a minimum period of 400 ns (maximum freq. 2.5 mhz), and is independent of the txclk and rxclk. m_mdio id/ ot g26 mii management data i/o. common for all four mii ports at up to 2.5 mhz. it is bi-directional between the zl50110/11/12/14 and the ethernet station management entity. data is passed synchronously with respect to m_mdc. table 9 - mii management interface package ball definition mii gmii tbi (pcs) table 8 - packet interface signal mapping - mii to gmii/tbi zl50110/11/12/14 data sheet 35 zarlink semiconductor inc. mii port 0 signal i/o package balls description m0_linkup_led o g24 on zl50110/4 ab23 on zl50111/2 led drive for mac 0 to indicate port is linked up. logic 0 output = led on logic 1 output = led off m0_active_led o ac26 led drive for mac 0 to indicate port is transmitting or receiving packet data. logic 0 output = led on logic 1 output = led off m0_gigabit_led o h22 led drive for mac 0 to indicate operation at gbps logic 0 output = led on logic 1 output = led off m0_refclk i d aa24 gmii/tbi - reference clock input at 125 mhz. can be used to lock receive circuitry (rx) to m0_gtxclk rather than recovering the rxclk (or rbc0 and rbc1). useful, for example, in the absence of valid serial data. note: in mii mode this pin must be driven with the same clock as m0_rxclk. m0_rxclk i u ab22 gmii/mii - m0_rxclk. accepts the following frequencies: 25.0 mhz mii 100 mbps 125.0 mhz gmii 1 gbps m0_rbc0 i u y24 tbi - m0_rbc0. used as a clock when in tbi mode. accepts 62.5 mhz, and is 180 out of phase with m0_rbc1. receive data is clocked at each rising edge of m1_rbc1 and m1_rbc0, resulting in 125 mhz sample rate. m0_rbc1 i u aa25 tbi - m0_rbc1 used as a clock when in tbi mode. accepts 62.5 mhz, and is 180 out of phase with m0_rbc0. receive data is clocked at each rising edge of m0_rbc1 and m0_rbc0, resulting in 125 mhz sample rate. table 10 - mii port 0 interface package ball definition zl50110/11/12/14 data sheet 36 zarlink semiconductor inc. m0_col i d y25 gmii/mii - m0_col. collision detection. this signal is independent of m0_txclk and m0_rxclk, and is asserted when a collision is detected on an attempted transmission. it is active high, and only specified for half-duplex operation. m0_rxd[7:0] i u [7] w25 [3] w26 [6] w24 [2] u22 [5] u23 [1] y26 [4] v24 [0] aa26 receive data. only half the bus (bits [3:0]) are used in mii mode. clocked on rising edge of m0_rxclk (gmii/mii) or the rising edges of m0_rbc0 and m0_rbc1 (tbi). m0_rxdv / m0_rxd[8] i d v25 gmii/mii - m0_rxdv receive data valid. active high. this signal is clocked on the rising edge of m0_rxclk. it is asserted when valid data is on the m0_rxd bus. tbi - m0_rxd[8] receive data. clocked on the rising edges of m0_rbc0 and m0_rbc1. m0_rxer / m0_rxd[9] i d v26 gmii/mii - m0_rxer receive error. active high signal indicating an error has been detected. normally valid when m0_rxdv is asserted. can be used in conjunction with m0_rxd when m0_rxdv signal is de-asserted to indicate a false carrier. tbi - m0_rxd[9] receive data. clocked on the rising edges of m0_rbc0 and m0_rbc1. m0_crs / m0_signal_detect i d u25 gmii/mii - m0_crs carrier sense. this asynchronous signal is asserted when either the transmission or reception device is non-idle. it is active high. tbi - m0_signal detect similar function to m0_crs. m0_txclk i u u24 mii only - transmit clock accepts the following frequencies: 25.0 mhz mii 100 mbps m0_txd[7:0] o [7] v21 [3] aa23 [6] w23 [2] w21 [5] w22 [1] y22 [4] y23 [0] aa22 transmit data. only half the bus (bits [3:0]) are used in mii mode. clocked on rising edge of m0_txclk (mii) or the rising edge of m0_gtxclk (gmii/tbi). mii port 0 signal i/o package balls description table 10 - mii port 0 interface package ball definition (continued) zl50110/11/12/14 data sheet 37 zarlink semiconductor inc. m0_txen / m0_txd[8] o v23 gmii/mii - m0_txen transmit enable. asserted when the mac has data to transmit, synchronously to m0_txclk with the first pre-amble of the packet to be sent. remains asserted until the end of the packet transmission. active high. tbi - m0_txd[8] transmit data. clocked on rising edge of m0_gtxclk. m0_txer / m0_txd[9] o v22 gmii/mii - m0_txer transmit error. transmitted synchronously with respect to m0_txclk, and active high. when asserted (with m0_txen also asserted) the zl501 10/11/12/14 will transmit a non-valid symbol, somewhere in the transmitted frame. tbi - m0_txd[9] transmit data. clocked on rising edge of m0_gtxclk. m0_gtx_clk o u21 gmii/tbi only - gigabit transmit clock output of a clock for gigabit operation at 125 mhz. mii port 0 signal i/o package balls description table 10 - mii port 0 interface package ball definition (continued) zl50110/11/12/14 data sheet 38 zarlink semiconductor inc. mii port 1 signal i/o package balls description m1_linkup_led o g23 on zl50110/4 f26 on zl50111/2 led drive for mac 1 to indicate port is linked up. logic 0 output = led on logic 1 output = led off m1_active_led o ab25 led drive for mac 1 to indicate port is transmitting or receiving packet data. logic 0 output = led on logic 1 output = led off m1_gigabit_led o g25 led drive for mac 1 to indicate operation at gbps. logic 0 output = led on logic 1 output = led off m1_refclk i d m22 gmii/tbi - reference clock input at 125 mhz. can be used to lock receive circuitry (rx) to m1_gtxclk rather than recovering the rxclk (or rbc0 and rbc1). useful, for example, in the absence of valid serial data. note: in mii mode this pin must be driven with the same clock as m1_rxclk. m1_rxclk i u m23 gmii/mii - m1_rxclk. accepts the following frequencies: 25.0 mhz mii 100 mbps 125.0 mhz gmii 1 gbps m1_rbc0 i u u26 tbi - m1_rbc0. used as a clock when in tbi mode. accepts 62.5 mhz and is 180c out of phase with m1_rbc1. receive data is clocked at each rising edge of m1_rbc1 and m1_rbc0, resulting in 125 mhz sample rate. m1_rbc1 i u t25 tbi - m1_rbc1 used as a clock when in tbi mode. accepts 62.5 mhz, and is 180 out of phase with m1_rbc0. receive data is clocked at each rising edge of m1_rbc1 and m1_rbc0, resulting in 125 mhz sample rate. m1_col i d r25 gmii/mii - m1_col. collision detection. this signal is independent of m1_txclk and m1_rxclk, and is asserted when a collision is detected on an attempted transmission. it is active high, and only specified for half-duplex operation. table 11 - mii port 1 interface package ball definition zl50110/11/12/14 data sheet 39 zarlink semiconductor inc. m1_rxd[7:0] i u [7] m25 [3] n25 [6] p26 [2] n24 [5] m24 [1] r26 [4] p25 [0] t26 receive data. only half the bus (bits [3:0]) are used in mii mode. clocked on rising edge of m1_rxclk (gmii/mii) or the rising edges of m1_rbc0 and m1_rbc1 (tbi). m1_rxdv / m1_rxd[8] i d m26 gmii/mii - m1_rxdv receive data valid. active high. this signal is clocked on the rising edge of m1_rxclk. it is asserted when valid data is on the m1_rxd bus. tbi - m1_rxd[8] receive data. clocked on the rising edges of m1_rbc0 and m1_rbc1. m1_rxer / m1_rxd[9] i d l21 gmii/mii - m1_rxer receive error. active high signal indicating an error has been detected. normally valid when m1_rxdv is asserted. can be used in conjunction with m1_rxd when m1_rxdv signal is de-asserted to indicate a false carrier. tbi - m1_rxd[9] receive data. clocked on the rising edges of m1_rbc0 and m1_rbc1. m1_crs / m1_signal_detect i d l23 gmii/mii - m1_crs carrier sense. this asynchronous signal is asserted when either the transmission or reception device is non-idle. it is active high. tbi - m1_signal detect similar function to m1_crs. m1_txclk i u l22 mii only - transmit clock accepts the following frequencies: 25.0 mhz mii 100 mbps m1_txd[7:0] o [7] r24 [3] r22 [6] p22 [2] p21 [5] r23 [1] t22 [4] t23 [0] r21 transmit data. only half the bus (bits [3:0]) are used in mii mode. clocked on rising edge of m1_txclk (mii) or the rising edge of m1_gtxclk (gmii/tbi). m1_txen / m1_txd[8] o p23 gmii/mii - m1_txen transmit enable. asserted when the mac has data to transmit, synchronously to m1_txclk with the first pre-amble of the packet to be sent. remains asserted until the end of the packet transmission. active high. tbi - m1_txd[8] transmit data. clocked on rising edge of m1_gtxclk. mii port 1 signal i/o package balls description table 11 - mii port 1 interface package ball definition (continued) zl50110/11/12/14 data sheet 40 zarlink semiconductor inc. m1_txer / m1_txd[9] o n23 gmii/mii - m1_txer transmit error. transmitted synchronously with respect to m1_txclk, and active high. when asserted (with m1_txen also asserted) the zl50110/11/12/14 will transmit a non-valid symbol, somewhere in the transmitted frame. tbi - m1_txd[9] transmit data. clocked on rising edge of m1_gtxclk. m1_gtx_clk o n21 gmii/tbi only - gigabit transmit clock output of a clock for gigabit operation at 125 mhz. mii port 2 - zl50111 and zl50112 variants only. note: this port must not be used to receive data at the same time as port 3, they are mutually exclusive. signal i/o package balls description m2_linkup_led o g23 led drive for mac 2 to indicate port is linked up. logic 0 output = led on logic 1 output = led off m2_active_led o ab24 led drive for mac 2 to indicate port is transmitting or receiving packet data. logic 0 output = led on logic 1 output = led off m2_rxclk i u aa19 mii only - receive clock. accepts the following frequencies: 25.0 mhz mii 100 mbps m2_col i d ae26 collision detection. this signal is independent of m2_txclk and m2_rxclk, and is asserted when a collision is detected on an attempted transmission. it is active high, and only specified for half-duplex operation. m2_rxd[3:0] i u [3] ad25 [1] ab21 [2] ac23 [0] ad24 receive data. clocked on rising edge of m2_rxclk. m2_rxdv i d aa20 receive data valid. active high. this signal is clocked on the rising edge of m2_rxclk. it is asserted when valid data is on the m2_rxd bus. table 12 - mii port 2 interface package ball definition mii port 1 signal i/o package balls description table 11 - mii port 1 interface package ball definition (continued) zl50110/11/12/14 data sheet 41 zarlink semiconductor inc. m2_rxer i d ac24 receive error. active high signal indicating an error has been detected. normally valid when m2_rxdv is asserted. can be used in conjunction with m2_rxd when m2_rxdv signal is de-asserted to indicate a false carrier. m2_crs i d ac25 carrier sense. this asynchronous signal is asserted when either the transmission or reception device is non-idle. it is active high. m2_txclk i u ad26 mii only - transmit clock accepts the following frequencies: 25.0 mhz mii 100 mbps m2_txd[3:0] o [3] ae25 [1] ac21 [2] ad23 [0] ae24 transmit data. clocked on rising edge of m2_txclk. m2_txen o ac22 transmit enable. asserted when the mac has data to transmit, synchronously to m2_txclk with the first pre-amble of the packet to be sent. remains asserted until the end of the packet transmission. active high. m2_txer o ab20 transmit error. transmitted synchronously with respect to m2_txclk, and active high. when asserted (with m2_txen also asserted) the zl50110/12 will transmit a non-valid symbol, somewhere in the transmitted frame. mii port 3 - zl50111 variant only note: this port must not be used to receive data at the same time as port 2, they are mutually exclusive. signal i/o package balls description m3_linkup_led o g24 led drive for mac 3 to indicate port is linked up. logic 0 output = led on logic 1 output = led off m3_active_led o ab26 led drive for mac 3 to indicate port is transmitting or receiving packet data. logic 0 output = led on logic 1 output = led off table 13 - mii port 3 interface package ball definition mii port 2 - zl50111 and zl50112 variants only. note: this port must not be used to receive data at the same time as port 3, they are mutually exclusive. signal i/o package balls description table 12 - mii port 2 interface package ball definition (continued) zl50110/11/12/14 data sheet 42 zarlink semiconductor inc. m3_rxclk i u k26 mii only - receive clock. accepts the following frequencies: 25.0 mhz mii 100 mbps m3_col i d j26 collision detection. this signal is independent of m3_txclk and m3_rxclk, and is asserted when a collision is detected on an attempted transmission. it is active high, and only specified for half-duplex operation. m3_rxd[3:0] i u [3] j22 [1] j24 [2] j23 [0] j25 receive data. clocked on rising edge of m3_rxclk. m3_rxdv i d j21 receive data valid. active high. this signal is clocked on the rising edge of m3_rxclk. it is asserted when valid data is on the m3_rxd bus. m3_rxer i d h26 receive error. active high signal indicating an error has been detected. normally valid when m3_rxdv is asserted. can be used in conjunction with m3_rxd when m3_rxdv signal is de-asserted to indicate a false carrier. m3_crs i d h24 carrier sense. this asynchronous signal is asserted when either the transmission or reception device is non-idle. it is active high. m3_txclk i u h25 mii only - transmit clock accepts the following frequencies: 25.0 mhz mii 100 mbps m3_txd[3:0] o [3] k23 [1] l25 [2] l26 [0] l24 transmit data. clocked on rising edge of m3_txclk. m3_txen o k24 transmit enable. asserted when the mac has data to transmit, synchronously to m3_txclk with the first pre-amble of the packet to be sent. remains asserted until the end of the packet transmission. active high. m3_txer o k25 transmit error. transmitted synchronously with respect to m3_txclk, and active high. when asserted (with m3_txen also asserted) the zl50111 will transmit a non-valid symbol, somewhere in the transmitted frame. mii port 3 - zl50111 variant only note: this port must not be used to receive data at the same time as port 2, they are mutually exclusive. signal i/o package balls description table 13 - mii port 3 interface package ball definition (continued) zl50110/11/12/14 data sheet 43 zarlink semiconductor inc. 3.4 external memory interface all external memory interface outputs are high impedance while system reset is low. if the external memory interface is unused, all input pins may be left unconnected. active low signals are designated by a # suffix, in acco rdance with the convention used in common memory data sheets. signal i/o package balls description ram_data[63:0] iu/ ot [63] ad7 [31] k3 [62] ae6 [30] k4 [61] af5 [29] j1 [60] ab8 [28] j2 [59] ac7 [27] j3 [58] ad6 [26] j4 [57] ae5 [25] h1 [56] af4 [24] h2 [55] af3 [23] h3 [54] ae4 [22] j5 [53] ad5 [21] g1 [52] aa8 [20] j6 [51] ab7 [19] h4 [50] af2 [18] g2 [49] ac6 [17] h5 [48] ae3 [16] g3 [47] ad4 [15] f1 [46] ac5 [14] g4 [45] aa7 [13] f2 [44] ab6 [12] f3 [43] ab5 [11] g5 [42] ac4 [10] e1 [41] ad3 [9] e2 [40] ae2 [8] g6 [39] aa5 [7] f5 [38] ab4 [6] f4 [37] ac3 [5] e3 [36] ad2 [4] e4 [35 ae1 [3] d1 [34] ad1 [2] e5 [33] w6 [1] d2 [32] y5 [0] d4 buffer memory data. synchronous to rising edge of system_clk. ram_parity[7:0] iu/ ot [7] l1 [3] l5 [6] l2 [2] l6 [5] l3 [1] k1 [4] l4 [0] k2 buffer memory parity. synchronous to rising edge of system_clk. bit [7] is parity for data byte [63:56], bit [0] is parity for data byte [7:0]. table 14 - external memory interface package ball definition zl50110/11/12/14 data sheet 44 zarlink semiconductor inc. ram_addr[19:0] o [19] r4 [9] p1 [18] t2 [8] n4 [17] t1 [7] n3 [16] p5 [6] n2 [15] r3 [5] m1 [14] r2 [4] m2 [13] p4 [3] m4 [12] r1 [2] m3 [11] p3 [1] m6 [10] p2 [0] m5 buffer memory address output. synchronous to rising edge of system_clk. ram_bw_a# o u2 synchronous byte write enable a (active low). must be asserted same clock cycle as ram_addr. enables ram_data[7:0]. ram_bw_b# o t3 synchronous byte write enable b (active low). must be asserted same clock cycle as ram_addr. enables ram_data[15:8]. ram_bw_c# o u3 synchronous byte write enable c (active low). must be asserted same clock cycle as ram_addr. enables ram_data[23:16]. ram_bw_d# o v2 synchronous byte write enable d (active low). must be asserted same clock cycle as ram_addr. enables ram_data[31:24]. ram_bw_e# o w1 synchronous byte write enable e (active low). must be asserted same clock cycle as ram_addr. enables ram_data[39:32]. ram_bw_f# o v3 synchronous byte write enable f (active low). must be asserted same clock cycle as ram_addr. enables ram_data[47:40]. ram_bw_g# o w2 synchronous byte write enable g (active low). must be asserted same clock cycle as ram_addr. enables ram_data[55:48]. ram_bw_h# o y1 synchronous byte write enable h (active low). must be asserted same clock cycle as ram_addr. enables ram_data[63:56]. ram_rw# o u4 read/write enable output read = high write = low signal i/o package balls description table 14 - external memory interface package ball definition (continued) zl50110/11/12/14 data sheet 45 zarlink semiconductor inc. 3.5 cpu interface all cpu interface signals are 5 v tolerant. all cpu interface outputs are high impedance while system reset is low. signal i/o package balls description cpu_data[31:0] i/ ot [31] af25 [15] aa16 [30] ab19 [14] ad19 [29] ad22 [13] ae20 [28] ae23 [12] ab17 [27] ac20 [11] af21 [26] af24 [10] ac17 [25] ae22 [9] ae19 [24] ad21 [8] aa15 [23] aa17 [7] ab16 [22] ab18 [6] ad18 [21] ac19 [5] af19 [20] ad20 [4] ae18 [19] af23 [3] ad17 [18] ae21 [2] af20 [17] af22 [1] ab15 [16] ac18 [0] af18 cpu data bus. bi-directional data bus, synchronously transmitted with cpu_clk rising edge. note: as with all ports in the zl50110/11/12/14 device, cpu_data[0] is the least significant bit (lsb). cpu_addr[23:2] i [23] ab13 [11] ad11 [22] ac13 [10] af10 [21] ad13 [9] ac11 [20] ae13 [8] ae10 [19] af12 [7] ad10 [18] ae12 [6] ab11 [17] ad12 [5] af9 [16] ac12 [4] ac10 [15] af11 [3] ae9 [14] ab12 [2] aa11 [13] ae11 [12] aa12 cpu address bus. address input from processor to zl50110/11/12/14, synchronously transmitted with cpu_clk rising edge. note: as with all ports in the zl50110/11/12/14 device, cpu_addr[2] is the l east significant bit (lsb). cpu_cs i u af14 cpu chip select. synchronous to rising edge of cpu_clk and active low. is asserted with cpu_ts _ale. must be asserted with cpu_oe to asynchronously enable the cpu_data output during a read, including dma read. cpu_we i ad14 cpu write enable. synchronously asserted with respect to cpu_clk rising edge, and active low. used for cpu writes from the processor to registers within t he zl50110/11/12/14. asserted one clock cycle after cpu_ts _ale. table 15 - cpu interface package ball definition zl50110/11/12/14 data sheet 46 zarlink semiconductor inc. cpu_oe i ae14 cpu output enable. synchronously asserted with respect to cpu_clk rising edge, and active low. used for cpu reads from the processor to registers within the zl50110/11/12/14. asserted one clock cycle after cpu_ts _ale. must be asserted with cpu_cs to asynchronously enable the cpu_data output during a read, including dma read. cpu_ts _ale i ae15 synchronous input with rising edge of cpu_clk. latch enable (ale), active high signal. asserted with cpu_cs , for a single clock cycle. cpu_sdack1 i af15 cpu/dma 1 acknowledge input. active low synchronous to cpu_clk rising edge. used to acknowledge request from zl50110/11/12/14 for a dma write transaction. only used for dma transfers, not for normal register access. cpu_sdack2 i ad15 cpu/dma 2 acknowledge input active low synchronous to cpu_clk rising edge. used to acknowledge request from zl50110/11/12/14 for a dma read transaction. only used for dma transfers, not for normal register access. cpu_clk i ac14 cpu powerquicc? ii bus interface clock input. 66 mhz clock, with minimum of 6 ns high/low time. used to time all host interface signals into and out of zl50110/11/12/14 device. signal i/o package balls description table 15 - cpu interface package ball definition (continued) zl50110/11/12/14 data sheet 47 zarlink semiconductor inc. cpu_ta ot ab14 cpu transfer acknowledge. driven from tri-state condition on the negative clock edge of cpu_clk following the assertion of cpu_cs. active low, asserted from the rising edge of cpu_clk. for a read, asserted when valid data is available at cpu_data. the data is then read by the host on the following rising edge of cpu_clk. for a write, is asserted when the zl50110/11/12/14 is ready to accept data from the host. the data is written on the rising edge of cpu_clk following the assertion. returns to tri-state from the negative clock edge of cpu_clk following the de-assertion of cpu_cs. cpu_dreq0 ot ac15 cpu dma 0 request output active low synchronous to cpu_clk rising edge. asserted by zl50110/11/12/14 to request the host initiates a dma write. only used for dma transfers, not for normal register access. cpu_dreq1 ot ae16 cpu dma 1 request active low synchronous to cpu_clk rising edge. asserted by zl50110/11/12/14 to indicate packet data is ready for transmission to the cpu, and request the host initiates a dma read. only used for dma transfers, not for normal register access. cpu_ireqo o af17 cpu interrupt 0 request (active low) cpu_ireq1 o ad16 cpu interrupt 1 request (active low) signal i/o package balls description table 15 - cpu interface package ball definition (continued) zl50110/11/12/14 data sheet 48 zarlink semiconductor inc. 3.6 system function interface all system function interface signals are 5 v tolerant. the core of the chip will be held in reset for 16 383 system_clk cycles after system_rst has gone high to allow the pll?s to lock. no chip access should occur at this time. signal i/o package balls description system_clk i u6 system clock input. the system clock frequency is 100 mhz. the quality of system_clk, or the oscillator that drives system_clk directly impacts the adaptive clock recovery performance. see section 6.3. system_rst i v4 system reset input. active low. the system reset is asynchronous, and causes all registers within the zl50110/11/12/14 to be reset to their default state. recommend external pull-up. system_debug i u5 system debug enable. this is an asynchronous signal that, when de-asserted, prevents the software assertion of the debug-freeze command, regardless of the internal state of registers, or any error conditions. active high. recommend external pull-down. table 16 - system function interface package ball definition zl50110/11/12/14 data sheet 49 zarlink semiconductor inc. 3.7 test facilities 3.7.1 administration, control and test interface all administration, control and test interface signals are 5 v tolerant. 3.7.2 jtag interface all jtag interface signals are 5 v tolerant, and conform to the requirements of ieee1149.1 (2001). the zl50111 and zl50112 share a common jtag id. t hey also share a common chip_id register value. signal i/o package balls description gpio[15:0] id/ ot [15] aa4 [7] aa2 [14] ab3 [6] y3 [13] ac2 [5] ab1 [12] ac1 [4] y2 [11] ab2 [3] w4 [10] y4 [2] v5 [9] w5 [1] aa1 [8] aa3 [0] w3 general purpose i/o pins. connected to an internal register, so customer can set user-defined parameters. bits [4:0] reserved at startup or reset for memory tapped delay line (tdl) setup. see the zl50110/11/12/14 programmers model for more details. recommend 5 kohm pulldown on these signals. test_mode[2:0] i d [2] af6 [1] ab9 [0] ac8 test mode input - ensure these pins are tied to ground for normal operation. 000 sys_normal_mode 001-010 reserved 011 sys_tristate_mode 100-111 reserved table 17 - administration/control interface package ball definition signal i/o package balls description jtag_trst i u ae7 jtag reset. asynchronous reset. in normal operation this pin should be pulled low. recommend external pull-down. jtag_tck i ad8 jtag clock - maximum frequency is 25 mhz, typically run at 10 mhz. in normal operation this pin should be pulled either high or low. recommend external pull-down. jtag_tms i u aa10 jtag test mode select. synchronous to jtag_tck rising edge. used by the test access port controller to set certain test modes. jtag_tdi i u af7 jtag test data input. synchronous to jtag_tck. jtag_tdo o ac9 jtag test data output. synchronous to jtag_tck. table 18 - jtag interface package ball definition zl50110/11/12/14 data sheet 50 zarlink semiconductor inc. 3.8 miscellaneous inputs 3.9 power and ground connections signal package balls description ic_gnd ad9, af8, r5, t4, ae8 internally connected. tie to gnd. ic_vdd_io af16 internally connected. tie to vdd_io. table 19 - miscellaneous inputs package ball definitions signal package balls description vdd_io j9 j10 j11 j12 j13 j14 j15 j16 j17 j18 k9 k18 l9 l18 m9 m18 n9 n18 p9 p18 r9 r18 t9 t18 u9 u18 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 3.3 v vdd power supply for io ring gnd a1 a13 a26 e22 f6 f21 k5 k22 l11 l12 l13 l14 l15 l16 m11 m12 m13 m14 m15 m16 n1 n5 n11 n12 n13 n14 n15 n16 n22 n26 p6 p11 p12 p13 p14 p15 p16 p24 r11 r12 r13 r14 r15 r16 t5 t11 t12 t13 t14 t15 t16 t24 aa6 aa21 ab10 af1 af13 af26 0 v ground supply vdd_core f7 f12 f15 f20 h6 h21 k6 k21 m21 n6 t21 v6 y6 y21 aa9 aa13 aa14 aa18 1.8 v vdd power supply for core region a1vdd t6 1.8 v pll power supply table 20 - power and ground package ball definition zl50110/11/12/14 data sheet 51 zarlink semiconductor inc. 3.10 zl50111, zl50112, zl50110 and za50114 internal connections 3.11 zl50112 internal connections 3.12 zl50112 auxiliary clocks 4.0 typical applications 4.1 leased line provision circuit emulation is typically used to support the provisi on of leased line services to customers using legacy tdm equipment. for example, figure 6 shows a leased line tdm service being carried across a packet network. the advantages are that a carrier can upgr ade to a packet switched network, whilst still mainta ining their existing tdm business. signal package balls description ic r6, ac16, ae17 internally connected. must leave open circuit. table 21 - no connection ball definition signal package balls description ic g21, f25, e26. g22 internally connected. must leave open circuit. table 22 - no connection ball definition signal package balls description aux2_clko[1:0] c17, c15 auxilia ry clock output. typically aux2_clko[1] is connected to aux2_clki[1] and aux2_clko[0] is connected to aux2_clki[0] through a zero ohm resistor. aux2_clki[1:0] e15, d15 auxilia ry clock input. typically aux2_clki[1] is connected to aux2_clko[1] and aux2_clki[0] is connected to aux2_clko[0] through a zero ohm resistor. aux1_clko[1:0] d16, a18 auxilia ry clock output. typically aux1_clko[1] is connected to aux1_clki[1] and aux1_clko[0] is connected to aux1_clki[0] aux1_clki[1:0] e16, b18 auxilia ry clock input. typically aux1_clki[1] is connected to aux1_clko[1] and aux1_clki[0] is connected to aux1_clko[0] table 23 - auxiliary clock ball definition zl50110/11/12/14 data sheet 52 zarlink semiconductor inc. the zl50110/11/12/14 is capable of handl ing circuit emulation of both structured t1, e1, and j2 links (e.g., for support of fractional circuits) and unstructured (or clear ch annel) t1, e1, j2, t3 and e3 links. the device handles the data-plane requirements of the pr ovider edge inter-working function (w ith the exception of the physical interfaces and line interface units). control plane functi ons are forwarded to the host processor controlling the zl50110/11/12/14 device. the zl50110/11/12/14 provides a per-stream clock recovery function, in unstructured mode, to reproduce the tdm service frequency at the egress of the packet network. this is required othe rwise the queue at the egress of the packet network will either fill up or empty, depending on whether the regenerat ed clock is slower or faster than the original. figure 6 - leased line services over a circuit emulation link 4.2 metropolitan area network aggregation the metro ethernet application, shown in figure 7, consists of the me tro ethernet service m odules sitting on the edge of the metro ethernet ring. the modules will connect ethernet circuits and tdm circuits to the metro ring. the zl50110/11/12/14 is used to emulate leased li ne tdm circuits over ethernet by establishing cesop connections over the metro ethernet ring between the mtus/mdus and the pstn. the use of cesop eliminates the need for a separate tdm network in the metro core, thereby enabling convergence on a unified ethernet network. figure 7 - metropolitan area network aggregation using cesop carrier network customer premises customer premises extract clock customer data ~ ~ f service f service tdm packet network tdm customer data tdm to packet f service provider edge interworking function provider edge interworking function queue metro core metropolitan access network (resilient packet ring or metro ethernet) multi-tenant units t1/e1 links campus cesop oc-3, ds3 cesop metro access metro access t1/e1 links zl50110/11/12/14 data sheet 53 zarlink semiconductor inc. 4.3 digital loop carrier the broadband digital loop carrier (bbdlc) application, shown in figure 8, consists of a bbdlc connected to the central office (co) by a dedicated fiber link running gi gabit ethernet (ge) rather th an by nxt1/e1 or ds3/e3. the zl50110/11/12/14 is used to emulate tdm circuits over ethernet by establishing cesop connections between the bbdlc and the co. at the co the native ip or ethern et traffic is split from the cesop connections at sent towards the packet network. multiple t1/e1 cesop connections from several bbdlc are aggregated in the co using a larger zl50110/11/12/14 varian t, converted back to tdm circuits, and connected to a class 5 switch destined towards the pstn. in this configuration t3/e3 services can also be prov ided. using cesop allows voice and data traffic to be converged onto a single link. figure 8 - digital loop carrier using cesop dedicated fiber links central office t1/e1 n x t1/e1 pstn ip broadband dlc pots digital loop carrier gige over fiber central office switch (class 5) ip edge router or multi-service switching platform n x gige gige over fiber cesop zl50110/11/12/14 data sheet 54 zarlink semiconductor inc. 4.4 remote concentrator the remote concentrator application, shown in figure 9, consists of a remote concentrators connected to the central office (co) by a dedicated fiber link running gi gabit ethernet (ge) or ether net over sonet (eos) rather than by nxt1/e1 or ds3/e3. the remote concentrators provide both tdm service and native ethernet service to the mtu/mdu. the zl50110/11/12/14 is used to emulate tdm circuits over ethernet by establishing cesop connections between the remote concentrator and the co. the native ip or ether net traffic is multiplexed with the cesop traffic inside the remote concentrator and sent across the same ge con nection to the co. at the co the native ip or ethernet traffic is split from the cesop connections at sent to wards the packet network. multiple t1/e1 cesop connections from several remote concentrators are aggregated in t he co using a larger zl50110/ 11/12/14 variant, converted back to tdm circuits, and connected to the pstn through a higher bandwidth tdm circuit such as oc-3 or stm-1. the use of cesop here allows the convergence of voice and data on a single access network based on ethernet. this convergence on ethernet, a packet technology, ra ther than sonet/sdh, a sw itched circuit technology, provides cost and operational savings. figure 9 - remote concentrator using cesop multi-tenant / multi-dwelling units dedicated fiber links central office (aggregation) remote concentrator ethernet 10/100 mbps remote concentrator ethernet 10/100 mbps stm1- 4 nx gige pstn ip t1/e1 links gige over fiber t1/e1 links t1/e1 links gige over fiber cesop zl50110/11/12/14 data sheet 55 zarlink semiconductor inc. 4.5 cell site backhaul the cell site backhaul application, shown in figure 10, consists of 2g, 2.5g and 3g base stations, co-located at a cell site, connected to their respective 2g, 2.5g base station controllers and 3g radio network controller. the traditional leased t1/e1 lines between the cell site and the base station controllers is now replaced by a packet network such as fixed wireless or gigabit ethernet (ge) fiber, that may be owned by the carrier or accessed through a service provider. the zl50110/11/12/14 would sit in a box either external to the base stations , or integrated in them, and would transparently carry multiple t1/e1s to the base st ation controllers/radio network controllers using cesop connections. at the base station controller location another zl50110/11/12/14 wo uld terminate the cesop connection and provide the t1/e 1 line to the controllers. the use of the zl50110/11/12/14 would allow for lower co st transport between the two locations, due to the replacement of the leased t1/e1 line cost. the cesop connection would allow the t1/e1 to meet the strict timing requirements for 3g base stations. each t1/e1 may be asynchronous should a service provider be backhauling t1/e1s from multiple carriers. figure 10 - cell site backhaul using cesop ds3/ oc3 packet switched network gige over fiber cesop 3g base station 2.5g base station 2g base station cesop atm over t1/e1 atm over t1/e1 tdm over t1/e1 3g radio network controller 2.5g base station controller atm over t1/e1 atm over t1/e1 2g base station controller tdm over t1/e1 ds3/ oc3 ds3/ oc3 co-located base stations cesop zl50110/11/12/14 data sheet 56 zarlink semiconductor inc. 4.6 equipment architecture example an equipment architecture example is shown in figure 11, supporting t1/e1 ports is shown at the board level using zarlink?s cesop processors. in this example, the equ ipment consists of three line cards and an uplink card connected to a packet backplane. the first line card supports up to 32 t1/e1 lines, containi ng up to 1024 ds0, for nx64 kbps structured data transfer (sdt) cesop connections. the t1/e1 lines are broken down into ds0 channels on an h.110 bus. the zl50110/11/12/14 establishes cesop connections, with eac h connection taking a number of ds0 channels from the h.110 bus. the third line card support up to 32 t1/e1 or 2 t3/e3 li nes for private line unstructur ed data transfer (udt) cesop connections. the t1/e1 lines are not te rminated on the card by are transparent ly packetized into individual cesop connections by the zl50110/11/12/14. the second line card supports multiple 10/100/1000 mbps ethernet ports for native internet, video and data service. the uplink card multiplexes the ethernet traffic from the three cards, and uplinks the cesop, internet, video and data traffic to the packet switched network (psn.) figure 11 - equipment example using cesop unstructured, asynchronous ces unstructured, asynchronous ces t3/e3 or t1/e1 liu up to 32 t1/e1 or 2 t3/e3 per port clock recovery ethernet phys optical interface & drivers t3/e3 or t1/e1 liu structured, synchronous ces structured, synchronous ces octal t1/e1 framers mt9072 h.110 / hmvip bus up to 32 t1/e1 or 1024 channel dpll output up to 32 streams cesop processor zl50111 cesop processor zl50111 t1/e1 lius gigabit ethernet switch mvtx2801 t1/e1 lius ethernet concentrator mvtx2601 mvtx2801 ethernet traffic voice and data services 2 ge 2 ge packet switched networks zl50110/11/12/14 data sheet 57 zarlink semiconductor inc. 5.0 functional description the zl50110/11/12/14 family provides the data-plane proces sing to enable constant bit rate tdm services to be carried over a packet switched network, such as an ether net, ip or mpls network. the device segments the tdm data into user-defined packets, and passes it transparently over the packet network to be reconstructed at the far end. this has a number of applications, including emulat ion of tdm circuits and packet backplanes for tdm-based equipment. figure 12 - zl50110/11/12/14 family operation note: the zl50110/11/12/14 does not suppo rt the transmission or reception of jumbo packets, or packet sizes larger than 1522 bytes. 5.1 block diagram a diagram of the zl50110/11/12/14 device is given in figure 13, which shows the major data flows between functional components. figure 13 - zl50110/11/12/14 data and control flows constant bit rate tdm link packet switched network constant bit rate tdm link zl5011x tdm-packet conversion zl5011x tdm-packet conversion tdm equipment tdm equipment interworking function interworking function transparent data flow between tdm equipment up to 32 t1, 32 e1, 8 j2, 2 t3 or 2 e3 port h.110, h-mvip, st-bus backplanes up to triple 100 mbps mii fast ethernet or dual redundant 1000 mbps gmii/tbi gigabit ethernet motorola powerquicc tm compatible off-chip packet memory 0-8 mbytes ssram jtag interface triple packet interface mac tdm formatter payload assembly tdm interface packet receive packet transmit admin. clock recovery jt ag test controller central task manager host interface dma control data flows control flows protocol engine memory management unit on-chip ram and ssram interface controller zl50110/11/12/14 data sheet 58 zarlink semiconductor inc. 5.2 data and control flows there are numerous combinations that can be implement ed to pass data through the zl50110/11/12/14 device depending on the application requirements. the task manage r can be considered the central pivot, through which all flows must operate. the flow is determined by the type field in the task message (see zl50110/11/12/14 programmers model). each of the 11 data flows uses the task manager to ro ute packet information to the next block or interface for onward transmission. this section des cribes the flows between the tdm inte rface, the packet interface and the task manager which are the main flow routes used in t he zl50110/11/12/14 family. for example, the tdm->tm flow is used in flow types 1, 3, 5, and 6, and th e tm->pkt flow is used in flow types 1, 3, and 9. flow number flow through device 1 tdm to (tm) to pe to (tm) to pkt 2 pkt to (tm) to pe to (tm) to tdm 3 tdm to (tm) to pkt 4 pkt to (tm) to tdm 5 tdm to (tm) to cpu 6 tdm to (tm) to pe to (tm) to cpu 7 cpu to (tm) to tdm 8 pkt to (tm) to cpu 9 cpu to (tm) to pkt 10 1 tdm to (tm) to tdm 11 1 1. this flow is for loopback test purposes only pkt to (tm) to pkt table 24 - standard device flows zl50110/11/12/14 data sheet 59 zarlink semiconductor inc. 5.3 tdm interface the zl50110/11/12/14 family offers the following types of tdm service across the packet network: unstructured services are fully asynchronous, and include full support for clock recove ry on a per stream basis. both adaptive and differential clock recovery mechanisms can be used. structured services are synchronous, with all streams driven by a common clock and frame reference. these services can be offered in two ways: ? synchronous master mode - the zl50110/11/12/14 provides a common clock and frame pulse to all streams, which may be locked to an incoming clock or frame reference ? synchronous slave mode - the zl50110/11/12/14 accepts a common external clock and frame pulse to be used by all streams in either mode, n x 64 kbps trunking is supported as detailed in ?structured payload order? on page 63. the zl50110/11/12/14 supports structured mode or unst ructured mode, however it d oes not support structured mode and unstructured mode at the same time, all ports are either structured or unstructured. in structured mode, all tdm inputs must be synchronous. in addition, it can be used with a variety of different pr otocols. it includes full support for the ietf rfcs for cesopsn (circuit emulation services over packet sw itched networks) and satop (structure-agnostic transport over packet) protocols. 5.3.1 tdm interface block the tdm access interface consists of up to 32 stream s (depending on variant), each with an input and an output data stream operating at eit her 1.544 mbps or 2.048 mbps. it contains tw o basic types of interface: unstructured clock and data, for interfacing directly to a line interface unit; or structured, framed data, for interfacing to a framer or tdm backplane. unstructured data is treated asynchronously, with every st ream using its own clock. clock recovery is provided on each output stream, to reproduce the tdm service frequency at the egress of the packet network. structured data is treated synchronously, i.e., all data streams are timed by the same clock and frame references. these can either be supplied from an external source (slave mode) or generat ed internally using the on-chip stratum 4/4e dpll (master mode). service type tdm interface interface type interfaces to unstructured asynchronous t1, e1, j2, e3 and t3 bit clock in and out data in and out line interface unit structured synchronous (n x 64 kbps) t1, e1 and j2 framed tdm data streams at 2.048 and 8.192 mbps bit clock out frame pulse out data in and out framers tdm backplane (master) bit clock in frame in data in and out framers tdm backplane (slave) table 25 - tdm services offered by the zl50110/11/12/14 family zl50110/11/12/14 data sheet 60 zarlink semiconductor inc. 5.3.2 structured tdm port data formats the zl50110/11/12/14 is programmable such that the fram e/clock polarity and clock alignment can be set to any desired combination. table 26 shows a brief summary of four different tdm formats; st-bus, h.110, h-mvip, and generic (synchronous mode only), for more information s ee the relevant specifications shown. there are many additional formats for tdm transmission not depicted in table 26, but the flexibilit y of the port will cover almost any scenario. the overall data format is se t for the entire tdm interface device, rath er than on a per stream basis. it is possible to control the polarity of the master clock and frame pulse outputs, independent of the chosen data format (used when operating in synchronous master mode). data format data rate (mbps) number of channels per frame clock freq. (mhz) nominal frame pulse width (ns) frame pulse polarity frame boundary alignment standard clock frame pulse st-bus 2.048 32 2.048 244 negative rising edge straddles boundary msan-126 rev b (issue 4) zarlink 2.048 32 4.096 244 negative falling edge straddles boundary 8.192 128 16.384 61 negative falling edge straddles boundary h.110 8.192 128 8.192 122 negative rising edge straddles boundary ectf h.110 h-mvip 2.048 32 2.048 244 negative rising edge straddles boundary h-mvip release 1.1a 2.048 32 4.096 244 negative falling edge straddles boundary 8.192 128 16.384 244 negative falling edge straddles boundary generic 2.048 32 2.048 488 positive rising edge rising edge of clock 8.192 128 8.192 122 positive rising edge rising edge of clock table 26 - some of the tdm port formats accepted by the zl50110/11/12/14 family zl50110/11/12/14 data sheet 61 zarlink semiconductor inc. 5.3.3 tdm clock structure the tdm interface can operate in two modes, synchronou s for structured tdm data, and asynchronous for unstructured tdm data. the zl50110/11/12/14 is capable of providing the tdm clock fo r either of the modes. the zl50110/11/12/14 supports clock recovery in both syn chronous and asynchronous modes of operation. in asynchronous operation each stream may have independent clock recovery. 5.3.3.1 synchronou s tdm clock generation in synchronous mode all 32 streams will be driven by a common clock source. when the zl50110/11/12/14 is acting as a master device, the source can either be the inte rnal dpll or an external pll. in both cases, the primary and secondary reference clocks are taken from either two tdm input clocks, or two exte rnal clock sources driven to the chip. the input clocks are then divided down where ne cessary and sent either to the internal dpll or to the output pins for connection to an external dpll. the dpll then provides the common clock and frame pulse required to drive the tdm streams. see ?dpll s pecification? on page 75 for further details. figure 14 - synchronous tdm clock generation when the zl50110/11/12/14 is acting as a slave device, the common clock and frame pulse signals are taken from an external device providing the tdm master function. 5.3.3.2 asynchronous tdm clock generation each stream uses a separate internal dco to provide an asynchronous tdm clock output. the dco can be controlled to recover the clock from the original tdm source depending on the timing algorithm used. 5.4 payload assembly data traffic received on the tdm access interface is samp led in the tdm interface block, and synchronized to the internal clock. it is then forwarded to the payload assemb ly process. the zl50110/11/12/14 payload assembler can handle up to 128 active packet streams or ?contexts? simultaneously. packet payloads are assembled in the format shown in figure 15 - on page 62. this meets the requi rements of the ietf cesopsn standard (rfc 5086). alternatively, packet payloads are assembled in the fo rmat shown in figure 17 - on page 64. this meets the requirements of the ietf satop standard (rfc 4553). the packet transmit (ptx) circuit adds layer 2 and lay er 3 protocol headers. t he chosen protocol header combination for addition by the ptx mu st not exceed 64 bytes. the exceptio n is context 127 (the 128th context), which must not exceed 56 bytes. frame clock tdm_clki[31:0] pll_se c pll_pri srs srd div div internal dpll prs prd tdm_clkip tdm_clkis zl50110/11/12/14 data sheet 62 zarlink semiconductor inc. contexts in the tdm to pkt direction are placed in t he update state when they are opened, pending the local clock source generation. if there is no local clock source to generate packets, the context will remain in the update state and cannot be closed. zl5011x design manual section ?13.1 understanding forcedelete? describes the procedure to close transmit contexts in the update state. when the payload has been assembled it is written in to the centrally managed memory, and a task message is passed to the task manager. 5.4.1 structured payload operation in structured mode a context may contain any number of 64 kbps channels. these channels need not be contiguous and they may be selected from any input stream. channels may be added or deleted dynamically from a context. this feature can be used to optimize bandwidth utilisation. modifications to the context are synchronised with the start of a new packet. the fixed header at the start of each packet is added by the pa cket transmit block. this consists of up to 64 bytes, containing the ethernet header, any upper layer protocol headers, and the two byte context descriptor field (see section below). the header is entirely user pr ogrammable, enabling the use of any protocol. the payload header and size must be chosen so that the over all packet size is not less than 64 bytes, the ethernet standard minimum packet size. where this is likely to be the case, the header or data must be padded (as shown in figure 15 and figure 17) to ensure the packet is lar ge enough. this padding is added by the zl50110/11/12/14 for most applications. figure 15 - zl50110/11/12/14 packet format - structured mode in applications where large payloads are being used, the payload size must be chosen such that the overall packet size does not exceed the maximum ethernet packet size of 1518 bytes (1522 bytes with vlan tags). figure 15 channel 1 channel 2 channel x data for tdm frame 1 heade r ethernet fcs tdm payload (constructed by payload assembler) data for tdm frame n channel 1 channel 2 channel x data for tdm frame 2 channel 1 channel 2 channel x ethernet header network layers (added by packet transmit) upper layers (added by protocol engine) e.g. ipv4, ipv6, mpls e.g. udp, l2tp, rtp, cesopsn, satop may include vlan tagging static padding (if required to meet minimum payload size) may also be placed in the packet header zl50110/11/12/14 data sheet 63 zarlink semiconductor inc. shows the packet format for structured tdm data, where the payload is split into frames, and each frame concatenated to form the packet. 5.4.1.1 structured payload order packets are assembled sequentially, with each channel pl aced into the packet as it arrives at the tdm access interface. a fixed order of channels is maintained (see figure 16), with channel 0 placed before channel 1, which is placed before channel 2. it is this order that allows the packet to be correctly disassembled at the far end. a context must contain only unique channel numbers. as such a context that contains the same channel from different streams, for example channel 1 from stream 2 and channel 1 from stream 5, would not be permitted. figure 16 - channel order for packet formation each packet contains one or more frames of tdm data, in sequential order. this groups the selected channels for the first frame, followed by the same set of channels for the subsequent frame, and so on. 5.4.2 unstructured payload operation in unstructured mode, the payload is not split by defined fram es or timeslots, so the packet consists of a continuous stream of data. each packet contains a programmable num ber of octets, as shown in figure 17. the number of octets in a packet need not be an integer number of frames. a typical value for n may be 192, as defined in the ietf pwe3 rfc. for example, consider mapping the unst ructured data of a 25 timeslot ds0 stream. the data for each t1 frame would normally consist of 193 bits, 192 data bits and 1 framing bit. if the payload consists of 24 octets it will be 1 bit short of a complete frames worth of da ta, if the payload consists of 25 octets it will be 7 bits over a complete frames worth of data. note: no alignment of the octets with the t1 framing structure can be assumed. figure 17 - zl50110/11/12/14 packet format - unstructured mode channel 0 channel 1 channel 2 channel 31 stream 0 channel 0 channel 1 channel 2 channel 31 stream 31 channel 0 channel 1 channel 2 channel 31 stream 1 channel 0 channel 1 channel 2 channel 31 stream 2 channel assembly order heade r n octets of data from unstructured stream note: no frame or channel alignmen t may include vlan tagging e.g. ipv4, ipv6, mpls e.g. udp, l2tp, rtp, cesopsn, satop tdm payload (constructed by payload assembler) 46 to 1500 bytes may also be placed in the packet header octet 1 octet 2 octet n ethernet header network layers (added by packet transmit) upper layers (added by protocol engine) ethernet fcs static padding (if required to meet minimum payload size) zl50110/11/12/14 data sheet 64 zarlink semiconductor inc. note: to change the packet size of a context, first clos e the context and then re-open the context with a new packet size. 5.5 protocol engine in general, the next processing block for tdm packets is the protocol engine. this handles the data-plane requirements of the main higher level pr otocols (layers 4 and 5) expected to be used in typical applications of the zl50110/11/12/14 family: udp, rtp, l2tp, cesopsn and satop. the protocol engine can add a header to the datagram containing up to 24 bytes. this header is lar gely static information, and is programmed directly by the cpu. it may contain a number of dynamic fields, incl uding a length field, checksum, sequence number and a timestamp. the location, and in some cases the length of these fields is also progra mmable, allowing the various protocols to be placed at variable locations within the header. 5.6 packet transmission packets ready for transmission are queued to the switch fabric interface by the queue manager. four classes of service are provided, allowing some packet streams to be prioritized over others. on transmission, the packet transmit block appends a programmable header, which has been set up in advance by the control processor. typically this contains the data-link and network layer heade rs (layers 2 and 3), such as ethernet, ip (versions 4 and 6) and mpls. 5.7 packet reception incoming data traffic on the packet interface is received by the macs. the well-formed packets are forwarded to a packet classifier to determine the dest ination. when a packet is successfully classified the destination can be the tdm interface, the lan interface or the host interface. tdm traffic is then further classified to determine the context it is intended for. each tdm interface context has an individual queue, and the tdm re-formatting pr ocess re-creates the tdm streams from the incoming packet streams. this queue is used as a jitter bu ffer, to absorb variation in packet delay across the network. the size of the jitter buffer can be pr ogrammed in units of tdm frames (i.e., steps of 125 s). there is also a queue to the host interface, allowing a tr affic flow to the host cpu for processing. again the host?s dma controller can be used to retrieve packet data and write it out into the cpu?s own memory. 5.8 tdm formatter at the receiving end of the packet network, the origin al tdm data must be re-constructed from the packets received. this is known as re-formatting, and follows t he reverse process from the payload assembler. the tdm formatter plays out the packets in the correct sequence, di recting each octet to the selected timeslot on the output tdm interface. when lost or late packets are detected, the tdm format ter plays out underrun data for the same number of tdm frames as were included in the missing packet. underrun data can either be the last value played out on that timeslot, or a pre-programmed value (e.g., 0xff). if the packet subsequently turns up it is discarded. in this way, the end-to-end latency through the system is maintained at a constant value. contexts in the packet to tdm direction are placed in the update state when they are opened, pending first packet arrival. if a packet never arrives the context will remain in the udpate st ate. zl5011x design manual section ?13.1 understanding forcedelete? describes the pr ocedure to close receive contexts in the update state. zl50110/11/12/14 data sheet 65 zarlink semiconductor inc. 6.0 clock recovery one of the main issues with circuit em ulation is that the clock used to drive the tdm link is not necessarily linked into the central office reference clock, and hence may be any value within the tolerance defined for that service. the reverse link may also be independently timed, and operating at a slightly different frequency. in the plesiochronous digital hierarchy the difference in clock frequencies between tdm links is compensated for using bit stuffing techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network. with a packet network, that connection between the i ngress and egress frequency is broken, since packets are discontinuous in time. from figur e 6, the tdm service frequency f service at the customer premises must be exactly reproduced at the egress of the packet network. the consequence of a long -term mismatch in frequency is that the queue at the egress of t he packet network will either fill up or empty, depending on whether the regenerated clock is slower or faster than the original. this will cause loss of data and degradation of the service. the zl50110/11/12/14 provides clock recovery function to reproduce the tdm service frequency at the egress of the packet network for structur ed and unstructured mode. two schem es are employed, depending on the availability of a common reference clock at eac h provider edge unit, diff erential and adaptive. the adaptive and differential algorithms assume that there are no bit errors in the received packet header sequence number or timestamp fields. if there are bit errors in the sequence number or timestamp fields, especially in the most significant bits, then it is likely to cause a te mporary degradation of the reco vered clock performance. it is advised to protect packets end-to-end (e .g., by using ethernet fcs) such that packets with bit errors are discarded and do not impact the recovered clock performance. the clock recovery itself is performed by software in the host processor, with support from on-chip hardware to gather the required statistics. 6.1 differential clock recovery for applications where the wander characteristics of th e recovered clock are very important, such as when the emulated circuit must be connected into the plesioch ronous digital hierarchy (p dh), the zl50110/11/12/14 also offers a differential clock recovery technique. this re lies on having a common reference clock available at each provider edge point. the differential algorithm assumes th at the common clock is always present. there is no internal holdover capability for the common clock source (e.g. tdm_clkip) . if the availability of the common clock can not be guaranteed, then it is recommended to use an external dpll with holdover capability to provide a clock source at all times. the external dpll may enter holdover while the common clock is absent to maintain a relatively close frequency to the original common clock. in a differential technique, the timing of data packet formatio n is sent relative to the common reference clock. since the same reference is available at the packet egress point and the packet size is fixed, the original service clock frequency can be recovered. this technique is unaffected by any low frequency components in the packet delay variation. the disadvantage is the requirement for a comm on reference clock at each end of the packet network, which could either be the central offi ce tdm clock, or provided by a glo bal position system (gps) receiver. zl50110/11/12/14 data sheet 66 zarlink semiconductor inc. figure 18 - differential clock recovery for in-band differential al gorithm, the zl50110/11/12/14 inserts the timestamp after the packet payload is fully assembled. the insertion-time may be in error by up to 8 ui of the nominal service clock (for example 8 * 488 ns of an e1 interface).this variable error will occur in unstruc tured mode only, and result in degradation of performance at the remote end, which uses the timestamps to recover a clock frequency. this error is most likely to occur when there are many asynchronous (pdh) cloc ks that are close in frequency. in this case it is recommended to used the zarlink proprietary in-band differential. also, for in-band differential clock recovery, the fr equency must be the same as the common clock frequency. 6.2 adaptive clock recovery for applications where there is no common reference clock between provider edge units, an adaptive clock recovery technique is provided. the adaptive clock recovery solution provided in the zarlink cesop products is a combination hardware and software. the chip contains a dco per tdm port in unstructur ed mode, that enables the recovery of up to 32 independent clocks. the timing algori thm resides in the api and runs out of the host processor. the basic information is transmitted using timestamps . current ces standards allow for using of timestamps. timestamps may be implied by the value of the sequenc e numbers, or it can be formatted as rtp timestamps. when a packet containing tdm data is sent, an rtp time stamp and/or sequence number is placed into the packet header. on arrival at the receiving device, the arrival time is noted in the form of a local timestamp, driven by the output clock of the tdm port it is destined for. the recovered clock at the egress point of the zl50110/11/12/14 is based on no n-linear filtering of the timestamps that are carried in the cesop packets. the performance of the clock recovery is greatly improved by applying these non-liner filtering techniques. the adaptive clock recove ry performance is dependent on the network configuration and operation, if th e loading of the network is cons trained, then the wa nder of the recovered clock will not exceed the specified limits. liu liu zl5011x source node zl5011x destination node timestamp generation timestamp extraction host cpu timing recovery dco data source clock data dest'n clock packets packets prs clock network zl50110/11/12/14 data sheet 67 zarlink semiconductor inc. figure 19 - adaptive clock recovery 6.3 system_clk considerations the quality of the 100 mhz system_clk or the oscillator that drives system_clk directly impacts the adaptive clock recovery performance. zarlink has a recommended osci llator and guide lines for the selection of an oscillator. please refer to zl5011x design manual section ?3.6 system clock block? before choosing an oscillator. zl5011x source node zl5011x destination node host cpu queue monitor dco source clock dest'n clock packets packets network queue time stamp zl50110/11/12/14 data sheet 68 zarlink semiconductor inc. 7.0 system features 7.1 latency the following lists the intrinsic proc essing latency of the zl50110/11/12/14 , regardless of the number of active channels or contexts. ? tdm to packet transmission processing latency less than 125 s ? packet to tdm transmission processing latency less than 250 s (unstructured) ? packet to tdm transmission processing latency less than 250 s (structured, more than 16 channels in context) ? packet to tdm transmission processing latency less than 375 s (structured, 16 or less channels in context) end-to-end latency may be estimated as the transmit la tency + packet network latency + receive latency. the transmit latency is the sum of the transmit processing and the num ber of frames per packet x 125 s. the receive latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to compensate for packet network pdv. the zl50110/11/12/14 is capable of creat ing an extremely low latency connecti on, with end to end delays of less than 0.5 ms, depending on user configuration. 7.2 loopback modes the zl50110/11/12/14 devices support loopback of t he tdm circuits and the circuit emulation packets. tdm loopback is achieved by first packetizing the tdm circuit as normal via the tdm interface and payload assembly blocks. the packetized data is then routed by the task manager bac k to the same tdm port via the tdm formatter and tdm interface. loopback of the emulated services is achieved by redirect ing classified packets from the packet receive blocks, back to the packet network. the packet transmit bloc ks are setup to strip the or iginal header and add a new header directing the packets back to the source. 7.3 host packet generation the control processor can generate packets directly, allowi ng it to use the network for out-of-band communications. this can be used for transmission of control data or networ k setup information, e.g., r outing information. the host interface can also be used by a local resource for network transmission of processed data. the device supports dual address dma transfers of pack ets to and from the cpu memory, using the host's own dma controller. table 27 illustra tes the maximum bandwidths achiev able by an external dma master. note 1: maximum bandwidths are the maximum the zl50110/11/12/14 devices can transfer under host control, and assumes only minimal packet processing by the host. note 2: combined figures assume the same amount of data is to be transferred each way. note 3: dma with external memory must use single packet mode. refer to zl5011x design manual for details. dma path packet size max bandwidth mbps 1 zl50110/11/12/14 to cpu only >1000 bytes 50 zl50110/11/12/14 to cpu only 60 bytes 6.7 cpu to zl50110/11/12/14 only >1000 bytes 60 cpu to zl50110/11/12/14 only 60 bytes 43 combined 2 >1000 bytes 58 (29 each way) combined 2 60 bytes 11 (5.5 each way) table 27 - dma maximum bandwidths zl50110/11/12/14 data sheet 69 zarlink semiconductor inc. 7.4 loss of service (los) during normal operation, a situation may arise where a lo ss of service occurs. this may be caused by a disruption in the transmission line due to engineering works or cabl e disconnection, for example. the locally detected los should be transferred across the emul ated t1/e1 to the far end. the far end, in turn, should propagate ais downstream. the handling of los over a cesop connection is typically performed using (setting/cl earing) the l bit in the cesopsn or satop control word of the packet header. refer to zl5011x design manual section ?3.1.1 connection to liu? for details on a variety of different ways that los may be handled in an application. 7.5 external memory requirement the zl50110/11/12/14 family includes a large amount of on -chip memory, such that for most applications, external memory will not be required. however, for certain combinations of header size, packet size and jitter buffer size, there may be a requirement for external memory. theref ore the device allows the connection of up to 8 mbytes of synchronous zbt-sram. the following charts show how much memory is required by the zl50111 (32 t1 streams) and the zl50110 (8 t1 streams) for a variety of packet sizes (expressed in numbe r of frames of tdm data) and jitter buffer sizes. it is assumed that each packet contains a fu ll ethernet/mpls/mpls/rtp/cesopsn header. figure 20 - external memory requirement for zl50111 external memory requirements for different packet sizes 32 t1 streams, with ethernet/mpls/mpls/rtp/cesopsn headers 0 1024 2048 3072 4096 5120 6144 7168 8192 4 8 16 32 64 128 256 jitter buffer size, ms external memory requirement, kbytes 1 frame packets 8 frame packets 16 frame packets 1 t3 stream (1 frame) zl50110/11/12/14 data sheet 70 zarlink semiconductor inc. figure 21 - external memory requirement for zl50110 7.6 gigabit ethernet - recommended co nfigurations note: in gmii/tbi mode only 1 gmac port may be used. the second gmac port is for redundancy purposes only. this section outlines connection methods for t he zl50110/11/12/14 in a gigabit ethernet environment recommended to ensure optimum performance. two areas are covered: ? central ethernet switch ? redundant ethernet switch external memory requirements for different packet sizes 8 t1 streams, with ethernet/mpls/mpls/rtp/cesopsn headers 0 1024 2048 3072 4096 5120 6144 7168 8192 4 8 16 32 64 128 256 jitter buffer size, ms external memory requirement, kbytes 1 frame packets 8 frame packets 16 frame packets zl50110/11/12/14 data sheet 71 zarlink semiconductor inc. 7.6.1 central ethernet switch figure 22 - gigabit ethernet c onnection - central ethernet switch tdm data and control packets are directed to the appr opriate zl50110/11/12/14 device through the ethernet switch. there is no limit on the numbe r of zl50110/11/12/14 devic es that can be connected in this configuration. gmii gmii zl5011x tdm gmii gmii zl5011x tdm gmii gmii zl5011x tdm gmii gmii zl5011x tdm ethernet switch network zl50110/11/12/14 data sheet 72 zarlink semiconductor inc. 7.6.2 redundant ethernet switch figure 23 - gigabit ethernet conn ection - redundant ethernet switch the central ethernet switch configuration can be extend ed to include a redundant switch connected to the second zl50110/11/12/14 gmii port. one port should be used for all the tdm-to-packet and packet-to-tdm data with the other port idle. if the current port fails t hen data must be transferred to the spare port. 7.7 power up sequence to power up the zl50110/11/12/14 the following procedure must be used: ? the i/o supply should lead the core supply, or both can be brought up together ? the i/o supply must never exceed the core supply by more than 2.0vdc ? the core supply must never exceed the i/o supply by more than 0.5vdc ? the system reset and the jtag reset must remain lo w until at least 100 s after the 100 mhz system clock has stabilised. note that if jtag reset is not used it must be tied low. this is illustrated in the diagram shown in figure 24. gmii gmii zl5011x tdm gmii gmii zl5011x tdm gmii gmii zl5011x tdm gmii gmii zl5011x tdm ethernet switch network ethernet switch network zl50110/11/12/14 data sheet 73 zarlink semiconductor inc. figure 24 - powering up the zl50110/11/12/14 7.8 jtag interface and board level test features the jtag interface is used to access the boundar y scan logic for board level production testing. 7.9 external component requirements 7.9.1 host processor zl50110/11/12/14 family offers di rect connection to powerquicc? ii (mpc8260) host processor and associated memory, but can support other processors with appropriate interface logic. 7.9.2 other components ? tdm framers and/or line interface units ? ethernet phy for each mac port ? optional zbt-sram for extended packet memory buffer depth 7.10 miscellaneous features ? system clock speed of 100 mhz ? host clock speed of up to 66 mhz ? debug option to freeze all internal state machines ? jtag (ieee1149) test access port ? 3.3 v i/o supply rail with 5 v tolerance ? 1.8 v core supply rail ? fully compatible with the mt90880/1/2/3 zarlink products rst sclk v dd i/o supply (3.3 v) core supply (1.8 v) 10 ns > 100 s <0.5 v dc t t t zl50110/11/12/14 data sheet 74 zarlink semiconductor inc. 7.11 test modes operation 7.11.1 overview the zl50110/11/12/14 family supports the following modes of operation. 7.11.1.1 system normal mode this mode is the device's normal operating mode. boundary sc an testing of the peripheral ring is accessible in this mode via the dedicated jtag pins. the jtag interface is compliant with the ieee std. 1149.1-2001; test access port and boundary scan architecture. each variant has it's own dedicated.bsdl file wh ich fully describes it's boundary scan architecture. 7.11.1.2 system tri-state mode all output and i/o output drivers are tri-stated allowing the device to be isolated when testing or debugging the development board. 7.11.2 test mode control the system test mode is selected using the dedicated dev ice input bus test_mode[2:0] as follows in table 28. 7.11.3 system normal mode selected by test_mode[2:0] = 3'b000. as the test_mode[2:0] inputs have inter nal pull-downs this is the default mode of operation if no external pull-up/downs are connec ted. the gpio[15:0] bus is captured on the rising edge of the external reset to provide internal bootstrap options. after the internal reset has been de-asserted the gpio pins may be configured by the adm modul e as either inputs or outputs. 7.11.4 system tri-state mode selected by test_mode[2:0] = 3'b011. all devic e output and i/o output drivers are tri-stated. system test mode test_mode[2:0] sys_normal_mode 3?b000 sys_tri_state_mode 3?b011 table 28 - test mode control zl50110/11/12/14 data sheet 75 zarlink semiconductor inc. 8.0 dpll specification the zl50110/11/12/14 family incorporat es an internal dpll that meets te lcordia gr-1244-core stratum 4/4e requirements, assuming an appropriate clock oscillator is connected to the system clock pin. it will meet the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency and mtie requirements fo r these specifications. in structured mode with the zl50110/11/12/14 device operating as a master the dpll is used to provide clock and frame reference signals to the internal and external tdm infrastr ucture. in structured mode, with the zl50110/11/12/14 device operating as a slave, the dpll is not used. all tdm clock generat ion is performed externally and the input streams are synchronised to the system clock by the tdm interface. th e dpll is not required in unstructured mode (hence it is not available) because the tdm clocks and frame signals are generated by internal dco?s assigned to each individual stream. 8.1 modes of operation it can be set into one of four operating modes: loc king mode, holdover mode, freerun mode and powerdown mode. 8.1.1 locking mo de (normal operation) the dpll accepts a reference signal from either a primar y or secondary source, providing redundancy in the event of a failure. these references should have the same nominal frequencies but do not need to be identical as long as their frequency offsets meet the appropriate stratum requir ements. each source is selected from any one of the available tdm input stream clocks (up to 32 on the zl50111 variant), or from the external tdm_clkip (primary) or tdm_clkis (secondary) input pins, as illus trated in figure 14 - on page 61. it is possible to supply a range of input frequencies as the dpll reference source, depicted in ta ble 29. the prd register value is the number (in hexadecimal) that must be programmed into the prd register within the dpll to obtain the divided down frequency at pll_pri or pll_sec. note 1: a prd/srd value of 0 will suppress the cl ock, and prevent it fr om reaching the dpll. note 2: ui means unit interval - in this ca se periods of the time signal. so 1ui on a 64 khz signal means 15.625 s, the period of the reference frequency. similarly 1023ui on a 4.096 mhz signal means 250 s. note 3: this input frequency is supported with the use of an external divide by 2. source input frequency (mhz) tolerance ( ppm) divider ratio prd/srd register value (hex) (note 1) frequency at pll_pri or pll_sec (mhz) maximum acceptable input wander tolerance (ui) (note 2) 0.008 30 1 1 0.008 1 1.544 130 1 1 1.544 1023 2.048 50 1 1 2.048 1023 4.096 50 1 1 4.096 1023 8.192 50 1 1 8.192 1023 16.384 50 1 1 16.384 1023 6.312 30 1 1 6.312 1023 22.368 20 2796 aec 0.008 1 (on 64k hz) 34.368 20 537 219 0.064 1 (on 64 khz) 44.736 (note 3) 20 699 2bb 0.064 1 (on 64 khz) table 29 - dpll input reference frequencies zl50110/11/12/14 data sheet 76 zarlink semiconductor inc. the maximum lock-in range can be programmed up to 372 ppm regardless of the input frequency. the dpll will fail to lock if the source input frequency is absent, if it is not of approximately the correc t frequency or if it is too jittery. see section 8.7 for further details. the applicatio n program interface (api) soft ware that accompanies the zl50110/11/12/14 family can be used to automatically se t up the dpll for the appropriate standard requirement. the dpll lock-in range can be programmed using the lock range register (see z l50110/11/12/14 programmers model document) in order to extend or reduce the captur e envelope. the dpll provides bit-error-free reference switching, meeting the specif ication limits in the telcordia gr-1244-core standard. if stratum 4/4e accuracy is not required, it is possible to use a mo re relaxed system clock tolerance. the dpll output consists of three signals; a common cloc k (comclk), a double-rate common clock (comclkx2), and a frame reference (8 khz). these are used to time the in ternal tdm interface, and hence the corresponding tdm infrastructure attached to the interface. the output cl ock options are either 2.048 mb ps (comclkx2 at 4.096 mbps) or 8.192 mbps (comclkx2 at 16.384 mbps ), determined by setup in the dpll control register. the frame pulse is programmable for polarity and width. 8.1.2 holdover mode in the event of a reference failure resulting in an absence of both the primary and secondary source, the dpll automatically reverts to holdover mode. the last valid frequency value recorded before failure can be maintained within the stratum 3 limits of 0.05 ppm. the hold va lue is wholly dependent on the drift and temperature performance of the system clock. for example, a 32 ppm oscillator may have a temperature coefficient of 0.1 ppm/c. thus a 10c ambient change since the dpll was last in the locking mode will change the holdover frequency by an additional 1 ppm, which is much greater t han the 0.05 ppm stratum 3 specification. if the strict target of stratum 3 holdover accuracy is not required, a less restrictive osci llator can be used for the system clock. holdover mode is typically used for a short period of time until network synchronisation is re-established. 8.1.3 freerun mode in freerun mode the dpll is programmed with a centre frequency, and can output that frequency within the stratum 3 limits of 4.6 ppm. to achieve this the 100 mhz system clock must have an absolute frequency accuracy of 4.6 ppm. the centre frequency is programmed as a fraction of the system clock frequency. 8.1.4 powerdown mode it is possible to ?power down? the dpll when it is not in use. for example, an unstructured tdm system, or use of an external dpll would mean the internal dpll could be sw itched off, saving power. the in ternal registers can still be accessed while the dpll is powered down. 8.2 reference monitor circuit there are two identical reference monitor circuits, o ne for the primary and one for the secondary source. each circuit will continually monitor its reference, and report the references validity. the validity criteria depends on the frequency programmed for the reference. a reference must meet all the following criteria to maintain validity: ? the ?period in specified range? check is performed regardless of the programmed frequency. each period must be within a range, which is programmable for the application. refer to the zl50110/11/12/14 programmers model for details. ? if the programmed frequency is 1.544 mhz or 2.048 mhz, t he ?n periods in specified range? check will be performed. the time taken for n cycles must be within a programmed range, typically with n at 64, the time taken for consecutive cycles must be between 62 and 66 periods of the programmed frequency. the fail flags are independent of the preferred option for primar y or secondary operation, will be asserted in the event of an invalid signal regardless of mode. zl50110/11/12/14 data sheet 77 zarlink semiconductor inc. 8.3 locking mode reference switching when the reference source the dpll is currently locking to becomes invalid, the dpll?s response depends on which one of the failure detect modes has been chosen: au todetect, forced primary, or forced secondary. one of these failure detect modes must be chosen via the fdm1:0 bits of the dom register. after a device reset via the system_reset pin, the autodetect mode is selected. in autodetect mode (automatic reference switching) if both references are valid the dpll will synchronise to the preferred reference. if the preferred reference becomes unreliable, the dpll c ontinues driving its output clock in a stable holdover state until it makes a switch to the back up reference. if the preferred reference recovers, the dpll makes a switch back to the preferred reference. if nece ssary, the switch back can be prevented by changing the preferred reference using the refsel bit in the dom r egister, after the switch to the backup reference has occurred. if both references are unreliable, the dpll will drive it s output clock using the stable holdover values until one of the references becomes valid. in forced primary mode, the dpll will synchronise to the primary reference only. the dpll will not switch to the secondary reference under any circumstances including the loss of the primary reference. in this condition, the dpll remains in holdover mode until the primary refer ence recovers. similarly in forced secondary mode, the dpll will synchronise to the secondary reference only, and will not switch to the primary reference. again, a failure of the secondary reference will cause the dpll to enter ho ldover mode, until such time as the secondary reference recovers. the choice of preferred reference has no effect in these modes. when a conventional pll is locked to its reference, ther e is no phase difference between the input reference and the pll output. for the dpll, the input references can have any phase relationship between them. during a reference switch, if the dpll output follows the phase of the new reference, a large phase jump could occur. the phase jump would be transferred to the tdm outputs. the dpll?s mtie (maximum time interval error) feature preserves the continuity of the dpll output so that it appears no reference sw itch had occurred. the mtie circuit is not perfect however, and a small time interval error is still incurred per reference switch. to align the dpll output clock to the nearest edge of the selected input reference, the mtie reset bit (mrst bit in the dom register) can be used. unlike some designs, switching between references whic h are at different nominal frequencies do not require intervention such as a system reset. 8.4 locking range the locking range is the input frequency range over which the dpll must be able to pull into synchronization and to maintain the synchronization. the lock ing range is programmable up to 372 ppm. note that the locking range relates to the system clock fr equency. if the external oscillator has a tolerance of -100 ppm, and the locking range is programmed to 200 ppm, the actual locking range is the programmed value shifted by the system clock tolerance to become -300 ppm to +100 ppm. 8.5 locking time the locking time is the time it takes the synchroniser to phase lock to the input signal. phase lock occurs when the input and output signals are not changing in phase wi th respect to each other (not including jitter). locking time is very difficult to determine be cause it is affected by many factors including: ? initial input to output phase difference ? initial input to output frequency difference ? dpll loop filter ? dpll limiter (phase slope) zl50110/11/12/14 data sheet 78 zarlink semiconductor inc. although a short phase lock time is des irable, it is not always achievable due to other synchroniser requirements. for instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases locking time; and a better (smaller) phase slope performance will increase locking time . additionally, the locking time is dependent on the p_shift value. the dpll loop filter and limiter have been optimised to meet the telcordia gr-1244-core jitter transfer and phase alignment speed requirements. the phase lock ti me is guaranteed to be no greater than 30 seconds when using the recommended stratum 3 and stratum 4/4e register settings. 8.6 lock status the dpll has a lock status indicator and a corresp onding lock change interrupt. the response of the lock status indicator is a function of the programmed lock dete ct interval (ldi) and lock detect threshold (ldt) values in the dpll_ldetect register. the ldt re gister can be programmed to set the ji tter tolerance level of the lock status indicator. to determine if the dpll has ac hieved lock the lock status indicator must be high for a period of at least 30 seconds. when the dpll loses lock the lock status indicator will go low after ldi x 125 s. 8.7 jitter the dpll is designed to withstand, and improv e inherent jitter in the tdm clock domain. 8.7.1 acceptance of input wander for t1(1.544 mhz), e1(2.048 mhz) and j2(6.312 mhz) input frequencies, the dpll will accept a wander of up to 1023ui pp at 0.1 hz to conform with the relevant specificati ons. for the 8 khz (frame rate) and 64 khz (the divided down output for t3/e3) input frequencie s, the wander acceptance is limited to 1 ui (0.1 hz). this principle is illustrated in table 29. 8.7.2 intrinsic jitter intrinsic jitter is the jitter produced by a synchronizer and measured at its output. it is measured by applying a jitter free reference signal to the input of the device, and measur ing its output jitter. intrinsic jitter may also be measured when the device is in a non synchronizing mode such as free running or holdover, by me asuring the output jitter of the device. intrinsic jitter is usually measured with various band-limiting filters, depending on the applicable standards. the intrinsic jitter in the dpll is reduced to less than 1 ns p-p 1 by an internal tapped delay line (tdl). 8.7.3 jitter tolerance jitter tolerance is a measure of the ability of a pll to oper ate properly without cycle slips (i.e. remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. the applied jitter magnitude and the ji tter frequency depends on the applicable standards. the dpll?s jitter tolerance can be programmed to m eet telcordia gr-1244-core ds1 reference input jitter tolerance requirements. 8.7.4 jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. i nput jitter is applied at va rious amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. 1. there are 2 exceptions to this. a) when reference is 8 khz, and reference frequency offset relative to the master is small, j itter up to 1 master clock period is possible, i.e. 10 ns p-p. b) in holdover mode, if a huge amount of jitter had been present prior to entering hol dover, then an additional 2 ns p-p is possible. zl50110/11/12/14 data sheet 79 zarlink semiconductor inc. since intrinsic jitter is always presen t, jitter attenuation will appear to be lo wer for small input jitter signals than larger ones. consequently, accurate jitter transfer functi on measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). the internal dpll is a first order type 2 component, so a fr equency offset doesn?t result in a phase offset. stratum 3 requires a -3 db frequency of less than 3 hz. the nature of the filter results in some peaking, resulting in a -3 db frequency of 1.9 hz and a 0.08 db peak with a system cl ock frequency of 100 mhz assuming a p_shift value of 2. the transfer function is illustrated in figure 25 and in more detail in figure 26. increasing the p_shift value increases the speed the dpll will lock to the required frequency and reduces the peak, but also reduces the tolerance to jitter - so the p_shift value must be progra mmed correctly to meet stratum 3 or stratum 4/4e jitter transfer characteristics. this is done automatically in the api. 8.8 maximum time interval error (mtie) in order to meet several standards requirements, the phase shift of the dpll output must be controlled. a potential phase shift occurs every time the dpll is re-arranged by changing reference source signal, or the mode. in order to meet the requirements of stratum 3, the dpll will shift phase by no more than 20 ns per re-arrangement. additionally the speed at which the change occurs is al so critical. a large step change in output frequency is undesirable. the rate of change is programmable using t he skew register, up to a maximum of 15.4 ns / 125 s (124 ppm). figure 25 - jitter transfer function zl50110/11/12/14 data sheet 80 zarlink semiconductor inc. figure 26 - jitter transfer function - detail 9.0 memory map and register definitions all memory map and register definitions are included in the zl50110/11/12/14 programmers model document. zl50110/11/12/14 data sheet 81 zarlink semiconductor inc. 10.0 dc characteristics * exceeding these figures may cause permanent damage. functional operation under these conditions is not guaranteed. voltage measurements are with respect to ground (v ss ) unless otherwise stated. * the core and pll supply voltages must never be allowed to exceed the i/o supply voltage by more than 0.5 v during power-up. fa ilure to observe this rule could lead to a high-current latch-up state, po ssibly leading to chip failure, if sufficient cross-supply cur rent is available. to be safe ensure the i/o supply voltage supply always rises earlier than the core and pll supply voltages. typical figures are at 25 c and are for design aid only, they are not guaranteed and not subject to production testing. voltage measurements are with respect to ground (v ss ) unless otherwise stated. absolute maximum ratings* parameter symbol min. max. units i/o supply voltage v dd_io -0.5 5.0 v core supply voltage v dd_core -0.5 2.5 v pll supply voltage v dd_pll -0.5 2.5 v input voltage v i -0.5 v dd + 0.5 v input voltage (5 v tolerant inputs) v i_5v -0.5 7.0 v continuous current at digital inputs i in - 10 ma continuous current at digital outputs i o - 15 ma package power dissipation pd - 3 w storage temperature ts -55 +125 c recommended operating conditions characteristics symbol min. typ. max. units test condition operating temperature t op -40 25 +85 c junction temperature t j -40 - 125 c positive supply voltage, i/o v dd_io 3.0 3.3 3.6 v positive supply voltage, core v dd_core 1.65 1.8 1.95 v positive supply voltage, core v dd_pll 1.65 1.8 1.95 v input voltage low - all inputs v il --0.8v input voltage high v ih 2.0 - v dd_io v input voltage high, 5v tolerant inputs v ih_5v 2.0 - 5.5 v zl50110/11/12/14 data sheet 82 zarlink semiconductor inc. dc electrical ch aracteristics - typical characteristics are at 1.8 v core, 3.3 v i/o, 25 c and typical processing. the min. and max. values are defined over all process conditions, from -40 to 125 c junction temperature, core voltage 1.65 to 1.95 v and i/o voltage 3.0 and 3.6 v unless otherwise stated. note 1: the io and core supply current worst case figures apply to different scenarios, e.g., internal or external memory and ca n not simply be summed for a tota l figure. for a clearer indication of power consumption, please refer to section 12.0 note 2: worst case assumes the maximum number of active contexts and channels, i.e., 128 contexts/1024 channels. figures are for the zl50111. for an indication of power consumption by the zl50110 and zl50114, please refer to section 12.0 and choose the appropriate memory configuration and number of contexts. characteristics symbol min. typ. max. units. test condition input leakage i leip 1 a no pull up/down v dd_io = 3.6 v output (high impedance) leakage i leop 2 a no pull up/down v dd_io = 3.6 v input capacitance c ip 1pf output capacitance c op 4pf pullup current i pu -27 a input at 0 v pullup current, 5 v tolerant inputs i pu_5v -110 a input at 0 v pulldown current i pd 27 a input at v dd_io pulldown current, 5 v tolerant inputs i pd_5v 110 a input at v dd_io core 1.8 v supply current i dd_core 950 ma note 1,2 pll 1.8 v supply current i dd_pll 1.30 ma i/o 3.3 v supply current i dd_io 120 ma note 1,2 input levels characteristics symbol min. typ. max. units test condition input low voltage v il 0.8 v input high voltage v ih 2.0 v positive schmitt threshold v t+ 1.6 v negative schmitt threshold v t- 1.2 v output levels characteristics symbol min. typ. max. units test condition output low voltage v ol 0.4 v i ol = 6 ma. i ol = 12 ma for packet interface (m*) pins and gpio pins. i ol = 24 ma for led pins. output high voltage v oh 2.4 v i oh = 6 ma. i oh = 12 ma for packet interface (m*) pins and gpio pins. i oh = 24 ma for led pins. zl50110/11/12/14 data sheet 83 zarlink semiconductor inc. 11.0 ac characteristics 11.1 tdm interface timing - st-bus the tdm bus either operates in slave mode, where the tdm clocks for each stream are provided by the device sourcing the data, or master mode, where the td m clocks are generated from the zl50110/11/12/14. 11.1.1 st-bus slave clock mode tdm st-bus slave timing specification data format parameter symbol min. typ. max. units notes st-bus 8.192 mbps mode tdm_clki period t c16ip 54 60 66 ns tdm_clki high t c16ih 27 - 33 ns tdm_clki low t c16il 27 - 33 ns st-bus 2.048 mbps mode tdm_clki period t c4ip - 244.1 - ns tdm_clki high t c4ih 110 - 134 ns tdm_clki low t c4il 110 - 134 ns all modes tdm_f0i width 8.192 mbps 2.048 mbps t foiw 50 200 - - - 300 ns tdm_f0i setup time t fois 5 - - ns with respect to tdm_clki falling edge tdm_f0i hold time t foih 5 - - ns with respect to tdm_clki falling edge tdm_sto delay t stod 1 - 20 ns with respect to tdm_clki load c l = 50 pf tdm_sti setup time t stis 5 - - ns with respect to tdm_clki tdm_sti hold time t stih 5 - - ns with respect to tdm_clki zl50110/11/12/14 data sheet 84 zarlink semiconductor inc. in synchronous mode the clock must be within the locki ng range of the dpll to functi on correctly ( 245 ppm). in asynchronous mode, the clock may be any frequency. figure 27 - tdm st-bus slave mode timing at 8.192 mbps figure 28 - tdm st-bus slave mode timing at 2.048 mbps channel 127 bit 1 channel 127 bit 0 channel 0 bit 7 channel 0 bit 6 ch0 bit7 channel 127 bit 1 channel 127 bit 0 channel 0 bit 7 t stod t stod t stod t stih t stis t stih t stis t stih t stis t foih t fois t c16ip tdm_ckli tdm_f0i tdm_sti tdm_sto channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 ch 31 bit 0 ch 0 bit 7 ch 0 bit 6 t stod t stod t foih t fois t stih t stis t foiw t c4ip t c2ip tdm_clki (2.048 mhz) tdm_clki (4.096 mhz) tdm_f0i tdm_sti tdm_sto zl50110/11/12/14 data sheet 85 zarlink semiconductor inc. 11.1.2 st-bus master clock mode figure 29 - tdm bus master mode timing at 8.192 mbps data format parameter symbol min. typ. max. units notes st-bus 8.192 mbps mode tdm_clko period t c16op 54.0 61.0 68.0 ns tdm_clko high t c16oh 23.0 - 37.0 ns tdm_clko low t c16ol 23.0 - 37.0 ns st-bus 2.048 mbps mode tdm_clko period t c4op 237.0 244.1 251.0 ns tdm_clko high t c4oh 115.0 - 129.0 ns tdm_clko low t c4ol 115.0 - 129.0 ns all modes tdm_f0o delay t fod - - 25 ns with respect to tdm_clko falling edge tdm_sto delay active-active t stod - - 5 ns with respect to tdm_clko falling edge tdm_sto delay active to hiz and hiz to active t dz , t zd - - 33 ns with respect to tdm_clko falling edge tdm_sti setup time t stis 5 - - ns with respect to tdm_clko tdm_sti hold time t stih 5 - - ns with respect to tdm_clko table 30 - tdm st-bus master timing specification channel 127 bit 0 channel 0 bit 7 channel 0 bit 6 b0 b7 b6 ch 127 bit 0 ch 0 bit 7 ch 0 bit 6 t stod t stod t fod t fod t stih t stis t stih t stis t c16op tdm_clko tdm_f0o tdm_sti tdm_sto zl50110/11/12/14 data sheet 86 zarlink semiconductor inc. figure 30 - tdm bus master mode timing at 2.048 mbps 11.2 tdm interface timing - h.110 mode these parameters are based on the h.110 specification from the enterprise computer telephony forum (ectf) 1997. note 1: tdm_c8 and tdm_frame signals are required to meet the same timing standards and so are not defined independently. note 2: tdm_c8 corresponds to pin tdm_clki. note 3: t doz and t zdo apply at every time-slot boundary. note 4: refer to h.110 standard from enterprise computer telephony forum (ectf) for the source of these numbers. note 5: the tdm_frame signal is centred on the rising edge of tdm_c8. a ll timing measurements are based on this rising edge point; tdm_frame corresponds to pin tdm_f0i. note 6: phase correction ( ) results from dpll timing corrections. parameter symbol min. typ. max. units notes tdm_c8 period t c8p 122.066- 122 122.074+ ns note 1 note 2 tdm_c8 high t c8h 63- - 69+ ns tdm_c8 low t c8l 63- - 69+ ns tdm_d output delay t dod 0 - 11 ns load - 12 pf tdm_d output to hiz t doz - - 33 ns load - 12 pf note 3 tdm_d hiz to output t zdo 0 - 11 ns load - 12 pf note 3 tdm_d input delay to valid t dv 0-83nsnote 4 tdm_d input delay to invalid t div 102 - 112 ns note 4 tdm_frame width t fp 90 122 180 ns note 5 tdm_frame setup t fs 45 - 90 ns tdm_frame hold t fh 45 - 90 ns phase correction f 0 - 10 ns note 6 table 31 - tdm h.110 timing specification channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 ch 31 bit 0 ch 0 bit 7 ch 0 bit 6 t stod t stod t fod t fod t stih t stis t c4op t c2op tdm_clko (2.048 mhz) tdm_clko (4.096 mhz) tdm_f0o tdm_sti tdm_sto zl50110/11/12/14 data sheet 87 zarlink semiconductor inc. figure 31 - h.110 timing diagram 11.3 tdm interface timing - h-mvip these parameters are based on the multi-vendor integrat ion protocol (mvip) specification for an h-mvip bus, release 1.1a (1997). positive transitions of tdm_c2 are sync hronous with the falling edges of tdm_c4 and tdm_c16 . the signals tdm_c2, tdm_c4 and tdm_c16 correspond with pins tdm_clki. the signals tdm_f0 correspond with pins tdm_f0i . the signals tdm_hds correspond with pins tdm_sti and tdm_sto. parameter symbol min. typ. max. units notes tdm_c2 period t c2p 487.8 488.3 488.8 ns tdm_c2 high t c2h 220 - 268 ns tdm_c2 low t c2l 220 - 268 ns tdm_c4 period t c4p 243.9 244.1 244.4 ns tdm_c4 high t c4h 110 - 134 ns tdm_c4 low t c4l 110 - 134 ns tdm_c16 period t c16p 60.9 61.0 61.1 ns tdm_c16 high t c16h 30 - 31 ns tdm_c16 low t c16l 30 - 31 ns tdm_hds output delay t pd --30nsat 8.192 mbps tdm_hds output delay t pd - - 100 ns at 2.048 mbps tdm_hds output to hiz t hzd --30ns table 32 - tdm h-mvip timing specification t c8p ts 127 bit 8 ts 0 bit 1 ts 0 bit 2 ts 127 bit 8 ts 0 bit 1 ts 0 bit 2 t dod t zdo t doz t div t dv t t fh t fp t fs t t c8l t t c8h tdm_c8 tdm_frame tdm_d input tdm_d output zl50110/11/12/14 data sheet 88 zarlink semiconductor inc. figure 32 - tdm - h-mvip timing di agram for 16 mhz clock (8.192 mbps) 11.4 tdm liu interface timing the tdm interface can be used to directly drive into a line interface unit (liu). the interface can work in this mode with e1, ds1, j2, e3 and ds3. the frame pulse is not present, just data and clock is transmitted and received. table 30 shows timing for ds3, which woul d be the most stri ngent requirement. tdm_hds input setup t s 30 - - ns tdm_hds input hold t h 30 - - ns tdm_f0 width t fw 200 244 300 ns tdm_f0 setup t fs 50 - 150 ns tdm_f0 hold t fh 50 - 150 ns parameter symbol min. typ. max. units notes tdm_txclk period t ctp 22.353 ns ds3 clock tdm_txclk high t cth 6.7 ns tdm_txclk low t ctl 6.7 ns tdm_rxclk period t crp 22.353 ns ds3 clock tdm_rxclk high t crh 9.0 ns tdm_rxclk low t crl 9.0 ns tdm_txdata output delay t pd 3-10ns tdm_rxdata input setup t s 6ns tdm_rxdata input hold t h 3ns table 33 - tdm - liu structured transmission/reception parameter symbol min. typ. max. units notes table 32 - tdm h-mvip timing specification (continued) t c16p ts 127 bit 7 ts 0 bit 0 ts 0 bit 1 ch 127 bit 7 ch 0 bit 0 t pd t hzd t h t s t fh t fs t fw t t c16h t t c16l tdm_c16 tdm_f0 tdm_hds input tdm_hds output zl50110/11/12/14 data sheet 89 zarlink semiconductor inc. figure 33 - tdm-liu structured transmission/reception 11.5 pac interface timing 11.6 packet interface timing data for the mii/gmii/tbi packet switching is based on specification ieee std. 802.3 - 2000. 11.6.1 mii transmit timing parameter symbol min. typ. max. units notes tdm_clkip high / low pulsewidth t cpp 10 - - ns tdm_clkis high / low pulsewidth t csp 10 - - ns table 34 - pac timing specification parameter symbol 100 mbps units notes min. typ. max. txclk period t cc -40-ns txclk high time t chi 14 - 26 ns txclk low time t clo 14 - 26 ns txclk rise time t cr --5ns txclk fall time t cf --5ns txclk rise to txd[3:0] active delay (txclk rising edge) t dv 1 - 25 ns load = 25 pf txclk to txen active delay (txclk rising edge) t ev 1 - 25 ns load = 25 pf table 35 - mii transmit timing - 100 mbps t pd t h t s t crl t crp t crh t ctl t ctp t cth tdm_txclk tdm_txdata tdm_rxclk tdm_rxdata zl50110/11/12/14 data sheet 90 zarlink semiconductor inc. figure 34 - mii transmit timing diagram txclk to txer active delay (txclk rising edge) t er 1 - 25 ns load = 25 pf parameter symbol 100 mbps units notes min. typ. max. table 35 - mii transmit timing - 100 mbps t dv t ev t ev t er t er t ch t cl t cc txclk txen txd[3:0] txer zl50110/11/12/14 data sheet 91 zarlink semiconductor inc. 11.6.2 mii receive timing figure 35 - mii receive timing diagram parameter symbol 100 mbps units notes min. typ. max. rxclk period t cc -40-ns rxclk high wide time t ch 14 20 26 ns rxclk low wide time t cl 14 20 26 ns rxclk rise time t cr --5ns rxclk fall time t cf --5ns rxd[3:0] setup time (rxclk rising edge) t ds 10 - - ns rxd[3:0] hold time (rxclk rising edge) t dh 5- -ns rxdv input setup time (rxclk rising edge) t dvs 10 - - ns rxdv input hold time (rxclk rising edge) t dvh 5- -ns rxer input setup time (rxcl edge) t ers 10 - - ns rxer input hold time (rxclk rising edge) t erh 5- -ns table 36 - mii receive timing - 100 mbps t dh t ds t dvh t dvs t erh t ers t chi t clo t cc rxclk rxdv rxd[3:0] rxer zl50110/11/12/14 data sheet 92 zarlink semiconductor inc. 11.6.3 gmii transmit timing figure 36 - gmii transmit timing diagram parameter symbol 1000 mbps units notes min. typ. max. gtxclk period t gc 7.5 - 8.5 ns gtxclk high time t gch 2.5 - - ns gtxclk low time t gcl 2.5 - - ns gtxclk rise time t gcr --1ns gtxclk fall time t gcf --1ns gtxclk rise to txd[7:0] active delay t dv 1.5 - 6 ns load = 25 pf gtxclk rise to txen active delay t ev 2-6ns load = 25 pf gtxclk rise to txer active delay t er 1-6ns load = 25 pf table 37 - gmii transmit timing - 1000 mbps t dv t ev t ev t er t er t ch t cl t cc gtxclk txen txd[3:0] txer zl50110/11/12/14 data sheet 93 zarlink semiconductor inc. 11.6.4 gmii receive timing figure 37 - gmii receive timing diagram parameter symbol 1000 mbps units notes min. typ. max. rxclk period t cc 7.5 - 8.5 ns rxclk high wide time t ch 2.5 - - ns rxclk low wide time t cl 2.5 - - ns rxclk rise time t cr --1ns rxclk fall time t cf --1ns rxd[7:0] setup time (rxclk rising edge) t ds 2- -ns rxd[7:0] hold time (rxclk rising edge) t dh 1- -ns rxdv setup time (rxclk rising edge) t dvs 2- -ns rxdv hold time (rxclk rising edge) t dvh 1- -ns rxer setup time (rxclk rising edge) t ers 2- -ns rxer hold time (rxclk rising edge) t erh 1- -ns table 38 - gmii receive timing - 1000 mbps t dh t ds t dvh t dvs t erh t ers t chi t clo t cc rxclk rxdv rxd[7:0] rxer zl50110/11/12/14 data sheet 94 zarlink semiconductor inc. 11.6.5 tbi interface timing note1: these measurements were obtained through simulation and lab measurement using a 10pf load. see zl5011x design manual section ?7.1.3.1 tbi interface timing? for proper operation when using the tbi interface. figure 38 - tbi transmit timing diagram parameter symbol 1000 mbps units notes min. typ. max. gtxclk period t gc 7.5 - 8.5 ns gtxclk high wide time t gh 2.5 - - ns gtxclk low wide time t gl 2.5 - - ns txd[9:0] output delay (gtxclk rising edge) t dv 0.1 - 2.4 load = 10 pf note 1 rcb0/rbc1 period t rc 15 16 17 ns rcb0/rbc1 high wide time t rh 5- -ns rcb0/rbc1 low wide time t rl 5- -ns rcb0/rbc1 rise time t rr --2ns rcb0/rbc1 fall time t rf --2ns rxd[9:0] setup time (rcb0 rising edge) t ds 2- -ns rxd[9:0] hold time (rcb0 rising edge) t dh 1- -ns refclk period t fc 7.5 - 8.5 ns refclk high wide time t fh 2.5 - - ns refclk low wide time t fl 2.5 - - ns table 39 - tbi timing - 1000 mbps /i/ /s/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /t/ /r/ /i/ t dv t gc gtxclk txd[9:0] signal_detect zl50110/11/12/14 data sheet 95 zarlink semiconductor inc. figure 39 - tbi receive timing diagram 11.6.6 management interface timing the management interface is common for all inputs and consists of a serial data i/o line and a clock line. note 1: refer to clause 22 in ieee8 02.3 (2000) standard for input/out put signal timing characteristics. note 2: refer to clause 22c.4 in ieee802.3 (2000) standard for output load description of mdio. figure 40 - management interface timing for ethernet port - read parameter symbol min. typ. max. units notes m_mdc clock output period t mp 1990 2000 2010 ns note 1 m_mdc high t mhi 900 1000 1100 ns m_mdc low t mlo 900 1000 1100 ns m_mdc rise time tmr - - 5 ns m_mdc fall time t mf --5ns m_mdio setup time (mdc rising edge) t ms 10 - - ns note 1 m_mdio hold time (m_mdc rising edge) t mh 0 - - ns note 1 m_mdio output delay (m_mdc falling edge) t md 1 - 300 ns note 2 table 40 - mac management timing specification /i/ /s/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /d/ /t/ /r/ /i/ t dh t ds t dh t ds t rc t rc rbc1 rbc0 rxd[9:0] signal_detect t mh t ms t mlo t mhi m_mdc m_mdio zl50110/11/12/14 data sheet 96 zarlink semiconductor inc. figure 41 - management interface timing for ethernet port - write 11.7 external me mory interface timing the timings for the external memory interface are based on the requirements of a zbt-sram device, with the system clock speed at 100 mhz. note 1: must be capable of driving two separate ram loads simultaneously. figure 42 - external ram read and write timing parameter symbol min. typ. max. units notes ram_data[63:0] output valid delay t rdv 1 - 4 ns load c l = 30 pf ram_rw/ram_addr[19:0] delay t rav 1 - 4 ns load c l = 30 pf note 1 ram_bw[7:0]# delay t rbw 1 - 4 ns load c l = 30 pf ram_data[63:0] setup time t rds 2- -ns ram_data[63:0] hold time t rdh 0.5 - - ns ram_parity[7:0] output valid delay t rpv 1 - 4 ns load c l = 30 pf ram_parity[7:0] setup time t rps 2- -ns ram_parity[7:0] hold time t rps 0.5 - - ns table 41 - external memory timing t md t mp mn_mdc mn_mdio n phase 1 phase 2 phase 3 phase 4 phase 5 phase 6 phase 7 phase 8 a1 a2 a3 a4 a5 a6 a7 a8 bw1 bw2 bw3 bw4 bw5 bw6 bw7 bw8 d(a1) q(a2) q(a3) d(a4) d(a5) q(a6) p(a1) p(a2) p(a3) p(a4) p(a5) p(a6) t rpv t rpv t rdv t rdv t rbw t rav t rav t rav t rav t rph t rps t rdh t rds t rdh t rds sclk ram_addr[19:0] ram_rw ram_bw[7:0] ram_data[63:0] ram_parity[7:0] a1 - read a2 - write a3 - write a4 - read a5 - read a6 - write a7 - read a8 - write zl50110/11/12/14 data sheet 97 zarlink semiconductor inc. 11.8 cpu interface timing note 1: load = 50 pf maximum note 2: the maximum value of t ctv may cause setup violations if directly connected to the mpc8260. see section 13.2 for details of how to accommodate this during board design. the actual point where read/write data is transferred occurs at the positive clock edge following the assertion of cpu_ta , not at the positive clock edge during the assertion of cpu_ta . the cpu_ta maximum assertion time is 4 s. parameter symbol min. typ. max. units notes cpu_clk period t cc 15.152 ns cpu_clk high time t cch 6ns cpu_clk low time t ccl 6ns cpu_clk rise time t ccr 4ns cpu_clk fall time t ccf 4ns cpu_addr[23:2] setup time t cas 4ns cpu_addr[23:2] hold time t cah 2ns cpu_data[31:0] setup time t cds 4ns cpu_data[31:0] hold time t cdh 2ns cpu_cs setup time t css 4ns cpu_cs hold time t csh 2ns cpu_we /cpu_oe setup time t ces 5ns cpu_we /cpu_oe hold time t ceh 2ns cpu_ts _ale setup time t cts 4ns cpu_ts _ale hold time t cth 2ns cpu_sdack1 /cpu_sdack2 setup time t cks 2ns cpu_sdack1 /cpu_sdack2 hold time t ckh 2nsnote 1 cpu_ta output valid delay t ctv 2 11.3 ns note 1, 2 cpu_dreq0 /cpu_dreq1 output valid delay t cwv 26nsnote 1 cpu_ireq0 /cpu_ireq1 output valid delay t crv 26nsnote 1 cpu_data[31:0] output valid delay t cdv 27nsnote 1 cpu_cs to output data valid t sdv 3.2 10.4 ns cpu_oe to output data valid t odv 3.3 10.4 ns cpu_clk(falling) to cpu_ta valid t otv 3.2 9.5 ns table 42 - cpu timing specification zl50110/11/12/14 data sheet 98 zarlink semiconductor inc. figure 43 - cpu read - mpc8260 figure 44 - cpu write - mpc8260 t otv t ctv t ctv t otv t sdv t odv t cdv t sdv t odv t cth t cts t ceh t ces t csh t css t cah t cas 0 or more cycles 0 or more cycles t cc note 1: cpu_data is valid when cpu_ta is asserted. cpu_data will remain valid while both cpu_cs and cpu_oe are asserted. cpu_ta will continue to be driven until cpu_cs is deasserted. cpu_clk cpu_addr[23:2] cpu_cs cpu_oe cpu_we cpu_ts _ale cpu_data[31:0] cpu_ta cpu_cs and cpu_oe must both be asserted to enable the cpu_data output. note 2: cpu_ts _ale is no more than one clock cycle width and it can be delayed by one clock cycle from cs assertion. note 3: the cpu_ta maximum assertion time is 4 s. t otv t ctv t ctv t otv t cdh t cds t cth t cts t ceh t ces t csh t css t cah t cas 0 or more cycles 0 or t cc 0 or more cycles 0 or more cycles note 1: following assertion of cpu_ta, cpu_cs may be deasserted. the mpc8260 will continue to assert cpu_cs until cpu_ta has been synchronized internally. cpu_ ta will continue to be driven until cpu_cs is finally deasserted. during continued assertion of cpu_cs, cpu_we and cpu_data may be removed. cpu_clk cpu_addr[23:2] cpu_cs cpu_oe cpu_we cpu_ts _ale cpu_data[31:0] cpu_ta note 2: cpu_ts _ale is no more than one clock cycle width and it can be delayed by one clock cycle from cs assertion. note 3:the cpu_ta maximum assertion time is 4 s. zl50110/11/12/14 data sheet 99 zarlink semiconductor inc. figure 45 - cpu dma read - mpc8260 figure 46 - cpu dma write - mpc8260 t otv t ctv t ctv t otv t sdv t odv t cdv t sdv t odv t cwv t cwv t cth t cts t ceh t ces t csh t css t ckh t cks 0 or more cycles 0 or more cycles t cc note 1: cpu_sdack2 must be asserted during the cycle shown. it may then be deasserted at any time. cpu_data is valid when cpu_ta is asserted (always timed as shown) . cpu_data will remain valid while cpu_cs and cpu_oe are asserted. cpu_ta will continue to be driven until cpu_cs is deasserted. cpu_cs and cpu_oe must both be asserted to enable cpu_clk cpu_dreq1 cpu_sdack2 cpu_cs cpu_oe cpu_we cpu_ts _ale cpu_data[31:0] cpu_ta the cpu_data output. note 2: cpu_dreq1 shown with positive polarity cpu_sdack1 shown with negative polarity t otv t ctv t ctv t otv t cwv t cwv t cdh t cds t cth t cts t ceh t ces t csh t css t ckh t cks 0 or more cycles 0 or more cycles t cc note 1: cpu_sdack1 must be asserted during the cycle shown. it may then be deasserted at any time. following assertion of cpu_ta (always timed as shown), cpu_cs may be deasserted. the mpc8260 will continue to assert cpu_cs until cpu_ta has been synchronized internally. cpu_ta will continue to be driven until cpu_cs is finally deasserted. during continued assertion of cpu_cs , cpu_we and cpu_data may be removed. cpu_clk cpu_dreq0 cpu_sdack1 cpu_cs cpu_oe cpu_we cpu_ts _ale cpu_data[31:0] cpu_ta note 2: cpu_dreq0 shown with positive polarity cpu_sdack1 shown with negative polarity zl50110/11/12/14 data sheet 100 zarlink semiconductor inc. 11.9 system function port note 1: the system clock frequency stability affects the holdover-ope rating mode of the dpll. holdover mode is typically used fo r a short duration while network synchronisation is temporarily disr upted. drift on the system clock directly affects the holdover mode accuracy. note that the absolute system clock accu racy does not affect the holdover accuracy, only the change in the system clock (system_clk) accuracy while in holdover. for example, if the syst em clock oscillator has a temperature coefficient of 0.1 ppm/oc, a 10oc change in temperature while the dpll is in will result in a frequency accuracy offset of 1ppm. the intrinsic frequency accuracy of the dpll holdov er mode is 0.06 ppm, excluding the system clock drift. note 2: the system clock frequency affects the operation of the dpll in free-run mode. in this mode, the dpll provides timing an d synchronisation signals which are based on the frequency of the accuracy of the master clock (i .e. frequency of clock output equals 8.192 mhz system_c lk accuracy 0.005 ppm). note 3: the absolute system_clk a ccuracy must be controlled to 30 ppm in synchronou s master mode to en able the internal dpll to function correctly. note 4: in asynchronous mode and in synchronous slave mode the dpll is not used. therefore the tolerance on system_clk may be relaxed slightly. note 5: the quality of system_clk, or the oscillator that drives system_clk directly impacts the adapti ve clock recovery performance. see section 6.3. parameter symbol min. typ. max. units notes system_clk frequency clk fr - 100 - mhz note 1, note 2 and note 5 system_clk accuracy (synchronous master mode) clk acs - - 30 ppm note 3 system_clk accuracy (synchronous slave mode and asynchronous mode) clk aca - - 200 ppm note 4 table 43 - system clock timing zl50110/11/12/14 data sheet 101 zarlink semiconductor inc. 11.10 jtag interface timing note 1: jtag_trst is an asynchronous signal. the setup time is for test purposes only. note 2: non test (other than jtag_tdi and jtag_tms ) signal input timing wi th respect to jtag_clk. note 3: non test (other than jtag_tdo) signal output with respect to jtag_clk. parameter symbol min. typ. max. units notes jtag_clk period t jcp 40 100 ns jtag_clk clock pulse width t low, t high 20 - - ns jtag_clk rise and fall time t jrf 0-3ns jtag_trst setup time t rstsu 10 - - ns with respect to jtag_clk falling edge. note 1 jtag_trst assert time t rst 10 - - ns input data setup time t jsu 5- -nsnote 2 input data hold time t jh 15 - - ns note 2 jtag_clk to output data valid t jdv 0 - 20 ns note 3 jtag_clk to output data high impedance t jz 0 - 20 ns note 3 jtag_tms, jtag_tdi setup time t tpsu 5- -ns jtag_tms, jtag_tdi hold time t tph 15 - - ns jtag_tdo delay t topdv 0 - 15 ns jtag_tdo delay to high impedance t tpz 0 - 15 ns table 44 - jtag interface timing zl50110/11/12/14 data sheet 102 zarlink semiconductor inc. figure 47 - jtag signal timing figure 48 - jtag clock and reset timing don't care dc hiz hiz t tpz t topdv t tph t tpsu t tph t tpsu t jcp t low t high jtag_tck jtag_tms jtag_tdi jtag_tdo t rstsu t rst t high t low jtag_tck jtag_trst zl50110/11/12/14 data sheet 103 zarlink semiconductor inc. 12.0 power characteristics the following graph in figure 49 illustrates typical po wer consumption figures for the zl50110/11/12/14 family. typical characteristics are at 1.8 v core, 3.3 v i/o, 25 c and typical processing. power is plotted against the number of active contexts, which is the dominant factor for power consumption. figure 49 - zl50110/11 / 12/14 power consumption plot zl501x power consumption (typical conditions) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 number of active contexts power (w) zl50110/11/12/14 data sheet 104 zarlink semiconductor inc. 13.0 design and layout guidelines this guide will provide information and guidance for pcb layouts when using the zl50110/11/12/14. specific areas of guidance are: ? high speed clock and data, outputs and inputs ? cpu_ta output 13.1 high speed clock & data interfaces on the zl50110/11/12/14 series of devices there are f our high-speed data interfaces that need consideration when laying out a pcb to ensure correct termination of traces and the reduction of crosst alk noise. the interfaces being: ? external memory interface ? gmac interfaces ? tdm interface ? cpu interface it is recommended that the outputs are su itably terminated using a series termin ation through a resistor as close to the output pin as possible. t he purpose of the series termination resistor is to reduce reflections on the line. the value of the series termination and the length of trace t he output can drive will depend on the driver output impedance, the characteristic impedance of the pcb trac e (recommend 50 ohm), the dist ributed trace capacitance and the load capacitance. as a general ru le of thumb, if the trac e length is less than 1/6th of the equivalent length of the rise and fall times, then a seri es termination may not be required. the equivalent length of rise time = rise time (ps) / delay (ps/mm) for example: typical fr4 board delay = 6.8 ps/mm typical rise/fall time for a zl50110/11/12/14 output = 2.5 ns critical track length = (1/6) x (2500/6.8) = 61 mm therefore tracks longer than 61 mm will require termination. as a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces, this is crosstalk. if the crosstalk is of sufficiently strong ampl itude, false data can be induced in the trace and therefore it should be minimized in the layout. the voltage that the extern al fields cause is proportional to the strength of the field and the length of the tr ace exposed to the field. therefore to mini mize the effect of crosstalk some basic guidelines should be followed. first, increase separation of sensitive signals, a rough ru le of thumb is that doubling the separation reduces the coupling by a factor of four. alternativ ely, shield the victim traces from the aggressor by either routing on another layer separated by a power plane (in a correctly decouple d design the power planes have the same ac potential) or by placing guard traces between the signals usually held ground potential. particular effort should be made to minimize crosstalk fr om zl50110/11/12/14 outputs and ensuring fast rise time to these inputs. in summary: ? place series termination resistors as close to the pins as possible ? minimize output capacitance ? keep common interface traces close to the same length to avoid skew ? protect input clocks and signals from crosstalk zl50110/11/12/14 data sheet 105 zarlink semiconductor inc. 13.1.1 external memory interface - special considerations during layout the timing of address, data and control are all related to the system clock which is also used by the external ssram to clock these signals. ther efore the propagation delay of the clock to the zl50110/11/12/14 and the ssram must be matched to within 250 ps, worst case condi tions. trace lengths of t heses signals must also be minimized (<100 mm) and matched to ensure correct operation under all conditions. 13.1.2 gmac interface - special considerations during layout the gmii interface passes data to and from the zl50110/11/ 12/14 with their related tran smit and receive clocks. it is therefore recommended that the trace lengths for transmit related sign als and their clock and the receive related signals and their clock are kept to the same length. by doing this the ske w between individual signals and their related clock will be minimized. 13.1.3 tdm interface - special considerations during layout although the data rate of this interface is low the out puts edge speeds share the charac teristics of the higher data rate outputs and therefore must be treated with the same care extended to the other interfaces with particular reference to the lower stream numbers which support the higher data rates. the tdm interface has numerous clocking schemes and as a result of this the input clo ck traces to the zl50110/11/ 12/14 devices should be treated with care. 13.1.4 summary particular effort should be made to minimize crosstalk fr om zl50110/11/12/14 outputs and ensuring fast rise time to these inputs. in summary: ? place series termination resistors as close to the pins as possible ? minimize output capacitance ? keep common interface traces close to the same length to avoid skew ? protect input clocks and signals from crosstalk 13.2 cpu ta output the cpu_ta output signal from the zl50110/11/12/14 is a critical handshake signal to the cpu that ensures the correct completion of a bus transaction between the two devices . as the signal is critical , it is recommend that the circuit shown in figure 50 - cpu_ta board circuit is implemented in systems operating above 40 mhz bus frequency to ensure robust operation under all conditions. the following external logic is required to implement the circuit: ? 74lcx74 dual d-type flip-flop (one section of two) ? 74lcx08 quad and gate (one section of four) ? 74lcx125 quad tri-state buffer (one section of four) ? 4k7 resistor x2 zl50110/11/12/14 data sheet 106 zarlink semiconductor inc. figure 50 - cpu_ta board circuit the function of the circuit is to extend the ta signal, to ensure the cpu corr ectly registers it. resistor r2 must be fitted to ensure correct operati on of the ta input to the processor. it is recommended that the logic is fitted close to the zl50110/11/12/14 and that th e clock to the 74lcx74 is derived from the same clock source as that input to the zl50110/11/12/14. 13.3 mx_linkup_led outputs the zl50111/2 and zl50110/4 have different mx_linkup_led pin assignments as shown in table 46. signal zl50111/2 pin zl50110/4 pin m0_linkup_led ab23 g24 m1_linkup_led f26 g23 m2_linkup_led g23 nc m3_linkup_led g24 nc table 45 - mx_linkup_led pin assignments d q cpu_clk cpu_ta from zl50110/11/12/14 cpu_cs to zl50110/11/14 to zl50110/11/12/14 +3v3 + 3v3 cpu_ta to cpu r1 r2 4k7 4k7 zl50110/11/12/14 data sheet 107 zarlink semiconductor inc. to generate a pin for pin compatible pcb for all three vari ants, the following stuffing options may be used as shown in figure 51. for the zl50111 and zl50112 variants, resi stors r4 and r6 are not po pulated. for the zl50110 and zl50114 variants, resistors r1, r2, r3 and r5 as well as leds for m2 and m3 are not populated. figure 51 - mx_linkup_led stuffing option m0/3_linkup_led (g24) m1/2_linkup_led (g23) m1_linkup_led (f26) m0_linkup_led (ab23) r1 r2 r3 r4 r5 r6 m3_linkup_led vdd_io m2_linkup_led m1_linkup_led m0_linkup_led vdd_io vdd_io vdd_io zl50110/1/4 zl50110/11/12/14 data sheet 108 zarlink semiconductor inc. table 46 lists the various component s that are used for each variant. component zl50111/2 zl50110/4 r1 - r2 - r3 - r4 - r5 - r6 - m0 led ? m1 led ? m2 led - m3 led - table 46 - mx_linkup_led stuffing option zl50110/11/12/14 data sheet 109 zarlink semiconductor inc. 14.0 reference documents 14.1 external standards/specifications ? ieee standard 1149.1-2001; test access port and boundary scan architecture ? ieee standard 802.3-2000; local and metropolitan networks csma/cd access method and physical layer ? ectf h.110 revision 1.0; hardwa re compatibility specification ? h-mvip (go-mvip) standard release 1.1a; multi-vendor in tegration protocol ? mpc8260aec/d revision 0.7; motorola mpc8260 family hardware specification ? rfc 768; udp ? rfc 791; ipv4 ? rfc 2460; ipv6 ? rfc 1889; rtp ? rfc 2661; l2tp ? rfc 1213; mib ii ? rfc 1757; remote network mo nitoring mib (for smiv1) ? rfc 2819; remote network mo nitoring mib (for smiv2) ? rfc 2863; interfaces group mib ? ccitt g.712; tdm timing specification (method 2) ? g.823; control of jitter/wander with digita l networks based on the 2.048 mbps hierarchy ? g.824; control of jitter/wander with digita l networks based on the 1.544 mbps hierarchy ? g.8261; timing and synchronization aspects in packet networks ? ansi t1.101 stratum 3/4 ? telcordia gr-1244-core stratum 3/4/4e ? rfc4553; structure-agnostic tdm over packet (satop) ? itu-t y.1413 tdm-mpls network interworking ? optional packet memory device - micron mt55l128l32p1 8 mb zbt-sram 14.2 zarlink standards ? msan-126 revision b, issue 4; st-b us generic device specification zl50110/11/12/14 data sheet 110 zarlink semiconductor inc. 15.0 glossary api application program interface atm asynchronous transfer mode cdp context descriptor protocol (the protocol used by zarlink?s mt9088x family of tdm-packet devices) cesop circuit emulation services over packet cesopsn circuit emulation services over packet sw itched networks (draft-ietf-pwe3-cesopsn) context a programmed connection of a number of tdm ti meslots assembled into a unique packet stream. cpu central processing unit dma direct memory access dpll digital phase locked loop dsp digital signal processor gmii gigabit media independent interface h.100/h.110 high capacity tdm backplane standards h-mvip high-performance multi-vendor integrat ion protocol (a tdm bus standard) ia implementation agreement ietf internet engineering task force ip internet protocol (version 4, rfc 791, version 6, rfc 2460) jtag joint test algorithms group (generally used to refer to a standard way of providing a board-level test facility) l2tp layer 2 tunneling protocol (rfc 2661) lan local area network liu line interface unit mac media access control mef metro ethernet forum mfa mpls and frame relay alliance mii media independent interface mib management information base mpls multi protocol label switching mtie maximum time interval error mvip multi-vendor integration pr otocol (a tdm bus standard) oc3 optical carrier 3 - 155.52 mbps leased line pdh plesiochronous di gital hierarchy pll phase locked loop prs primary reference source prx packet receive zl50110/11/12/14 data sheet 111 zarlink semiconductor inc. pstn public switched telephone circuit ptx packet transmit pwe3 pseudo-wire emulation edge to edge (a working group of the ietf) qos quality of service rtp real time protocol (rfc 1889) pe protocol engine satop structure-agnostic transport over packet ssram synchronous static random access memory st bus standard telecom bus, a standard interface for tdm data streams tdl tapped delay line tdm time division multiplexing udp user datagram protocol (rfc 768) ui unit interval vlan virtual local area network wfq weighted fair queuing zbt zero bus turnaround, a type of synchronous sram c zarlink semiconductor 2003 all rights reserved. issue apprd. date acn package code previous package codes 1 213837 12dec02 2 19aug03 www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of prod uct or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any pu rpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to pe rform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a license under the philips i 2 c patent righ ts to use th ese components in and i 2 c syste m, pro vided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl, the zarlink semiconductor logo and the legerity logo and combinations thereof, voiceedge, voiceport, slac, islic, islac and voicepath are trademarks of zarlink semiconductor inc. technical documentation - not for resale for more information ab out all zarlink products visit our web site at |
Price & Availability of ZL50111GAG2
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |